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Engineering letters

Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits.

Mozammel H. A. Khan

Published Jan 1, 2008• 33 citations
OpenAlex

Abstract

Abstract—Quantum computer algorithms require an ‘oracle’ as an integral part. An oracle is a reversible quantum Boolean circuit, where the inputs are kept unchanged at the outputs and the functional outputs are realized along ancillary input constants (0 or 1). Recently, a nearest neighbour template based synthesis method of quantum Boolean circuits has been proposed to overcome the adjacency requirement of the input qubits of physical quantum gates. The method used SWAP gates to bring the input qubits of quantum CNOT or C 2 NOT gates adjacent. In this paper, we propose cost reduction techniques such as ancillary constant determination to reduce the number of NOT gates and variable ordering and product grouping to reduce the number of SWAP gates required in nearest neighbour template based synthesis. The proposed approach significantly reduces the quantum realization cost of the synthesized quantum Boolean circuit than that of the original nearest neighbour template based synthesis. Index Terms — Ancillary constant determination, nearest neighbour template, product grouping, quantum Boolean circuit, fixed polarity Reed-Muller expression, reversible logic, variable ordering I.

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arXiv:1112.0564•Dec 2, 2011•48 citations
Abstract—Quantum computer algorithms require an ‘oracle’ as an integral part. An oracle is a reversible quantum Boolean circuit, where the inputs are kept unchanged at the outputs and the functional outputs are realized along ancillary input constants (0 or 1). Recently, a nearest neighbour template based synthesis method of quantum Boolean circuits has been proposed to overcome the adjacency requirement of the input qubits of physical quantum gates. The method used SWAP gates to bring the input qubits of quantum CNOT or C 2 NOT gates adjacent. In this paper, we propose cost reduction techniques such as ancillary constant determination to reduce the number of NOT gates and variable ordering and product grouping to reduce the number of SWAP gates required in nearest neighbour template based synthesis. The proposed approach significantly reduces the quantum realization cost of the synthesized quantum Boolean circuit than that of the original nearest neighbour template based synthesis. Index Terms — Ancillary constant determination, nearest neighbour template, product grouping, quantum Boolean circuit, fixed polarity Reed-Muller expression, reversible logic, variable ordering I.
Abstract—Quantum Boolean circuit synthesis issues are becoming a key area of research in the domain of quantum computing. For gate-level synthesis, minterm based and Reed-Muller canonical decomposition techniques are adopted as common approaches. Physical implementation of quantum circuits have inherent constraints and hence nearest neighbour template of input lines is gaining importance. In this work, we present a brief analysis of the various Fixed Polarity Reed Muller (FPRM) expressions for a given quantum Boolean circuit and also introduce the rules for the nearest neighbour template-based synthesis of these forms. The corresponding circuit costs are evaluated.
Quantum Boolean circuit (QBC) synthesis issues are becoming a key area of research in the domain of quantum computing. While Minterm gate based synthesis and Reed-Muller based canonical decomposition techniques are adopted commonly, nearest neighbor synthesis technique for QBC utilizes the quantum logic gates involving only the adjacent target and control qbits for a given quantum network. Instead of Quantum Boolean circuit synthesis using (SNOT gate, we have chosen the template-based technique for synthesis of QBC. This work defines new minimization rules using nearest neighbor templates, which results in reduced number of quantum gates and circuit levels. The need of proper relative placements of the quantum gates in order to achieve the minimum gate configuration has also been discussed.
With the advancement of technological footprints, high-end computation techniques, like quantum computation, have made significant progress in the design industry. Although quantum computation has proved itself as the next-generation computing paradigm, it is facing several design challenges, and one such design issue is in the form of the Nearest Neighbour (NN)t. This much-talked NN property demands the qubits in operating quantum gates to be adjacent, and a circuit should satisfy this NN property to be eligible for implementation. Considering the importance of NN enforcement in implementing circuits, we introduce a synthesis approach for the efficient transformation of reversible circuits to equivalent LNN representations. Our main focus in this work is to minimize the use of SWAP gates in designing NN-satisfied MCT-based reversible circuits. Towards transforming input circuits to LNN architecture, we have exploited a template matching scheme followed by two-qubit reordering policies, global and local, to improve the NN designs and reduce SWAP utilization. In finding the global solution, here we have used a dynamic programming algorithm where the initial order of qubit lines gets changed, while a heuristic-based SWAP placement function is used for finding a local qubit order sequence. The proposed synthesis workflow has been tested over an extensive set of benchmark functions, and comparison with the reported design approaches showed a substantial reduction in cost parameters.
Real quantum computing technologies have different restrictions and constraints which need to be considered during circuit synthesis. In certain technologies, only physically adjacent qubits can interact. It is common to use a pair of SWAP gates to bring the control and target qubits of any quantum gate to adjacent lines and maintain correct circuit functionality. This paper introduces a new method to synthesize linear nearest neighbor quantum circuit on the base of the analysis of quantum state in circuit. For all 3-qubit quantum circuit, experimental results shows that our algorithm can reduce the quantum cost by approximately 30% on average compared with one recent proposed method.
Abstract The construction of quantum computers is based on the synthesis of low-cost quantum circuits. The quantum circuit of any Boolean function expressed in a Positive Polarity Reed-Muller (PPRM) expansion can be synthesized using Multiple-Control Toffoli (MCT) gates. This paper proposes two algorithms to construct a quantum circuit for any Boolean function expressed in a PPRM expansion. The Boolean function can be expressed with various algebraic forms, so there are different quantum circuits can be synthesized for the Boolean function based on its algebraic form. The proposed algorithms aim to map the MCT gates into the NCV gates for any quantum circuit by generating a simple algebraic form for the Boolean function. The first algorithm generates a special algebraic form for any Boolean function by rearrangement of terms of the Boolean function according to a predefined degree of term d term , then synthesizes the corresponding quantum circuit. The second algorithm applies the decomposition methods to decompose MCT circuit into its elementary gates followed by applying a set of simplification rules to simplify and optimize the synthesized quantum circuit. The proposed algorithms achieve a reduction in the quantum cost of synthesized quantum circuits when compared with relevant work in the literature. The proposed algorithms synthesize quantum circuits that can applied on IBM quantum computer.
Linear Nearest Neighbor (LNN) synthesis in reversible circuits has emerged as an important issue in terms of technological implementation for quantum computation. The objective is to obtain a LNN architecture with minimum gate cost. As achieving optimal synthesis is a hard problem, heuristic methods have been proposed in recent literature. In this work we present a graph partitioning based approach for LNN synthesis with reduction in circuit cost. In particular, the number of SWAP gates required to convert a given gate-level quantum circuit to its equivalent LNN configuration is minimized. Our algorithm determines the reordering of indices of the qubit line(s) for both single control and multiple controlled gates. Experimental results for placing the target qubits of Multiple Controlled Toffoli (MCT) library of benchmark circuits show a significant reduction in gate count and quantum gate cost compared to those of related research works.