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西北工业大学学报

基于改进的整数量化 LDPC 码分层译码算法

Lingling Lao, 李立欣, 朱梦, 张会生

Published Jan 1, 2014• 0 citations
OpenAlex

Abstract

LDPC码分层译码算法在进行整数量化操作时，存储单元的限制会导致译码信息的溢出。本文系统分析了溢出错误的原因，并提出了两种改进的分层译码方案，错误部分消除方案（ partially eliminating errors scheme，PEES）和不同比特量化方案（different bit quantization scheme，DBQS）。两种改进方案分别从消除部分错误和避免溢出错误的角度来改进译码性能，且硬件实现时只需增加一定数量的加法器和移位操作。通过对不同码长、不同量化比特的LDPC码进行仿真，结果表明，2种方案均有效地抑制了溢出错误，与基于全精度浮点数运算的修正算法相比，在误码率为1．0＆#215;10－4时，分别仅有约1 dB和1．8 dB的性能损耗。

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IEEE Transactions on Circuits and Systems I Regular Papers•Feb 26, 2009•80 citations
LDPC码分层译码算法在进行整数量化操作时，存储单元的限制会导致译码信息的溢出。本文系统分析了溢出错误的原因，并提出了两种改进的分层译码方案，错误部分消除方案（ partially eliminating errors scheme，PEES）和不同比特量化方案（different bit quantization scheme，DBQS）。两种改进方案分别从消除部分错误和避免溢出错误的角度来改进译码性能，且硬件实现时只需增加一定数量的加法器和移位操作。通过对不同码长、不同量化比特的LDPC码进行仿真，结果表明，2种方案均有效地抑制了溢出错误，与基于全精度浮点数运算的修正算法相比，在误码率为1．0＆#215;10－4时，分别仅有约1 dB和1．8 dB的性能损耗。
针对Tanner图中圈的增加会影响码的性能的问题，提出了一种递归构造低密度校验（LDPC）码的方法。该方法利用一个短的LDPC码的校验矩阵作为其母矩阵，在此基础上采用循环置换矩阵构造一个长的LDPC码。通过对循环转置矩阵的参数进行约束，可以保证所构造的长码的Tanner图中指定长度的圈的个数等于或者小于其短码，且可以构造规则或者非规则的LDPC码。．仿真结果表明，采用该方法构造的LDPC码具有较低的误码平台，其性能与好的随机LDPC码几乎相同。
For the implementation of low-density parity-check (LDPC) decoders, the associated error performance and the complexity are significantly affected by the number of quantization bits used. In this paper, we propose an adaptive quantization scheme, which uses different quantization schemes at different iteration numbers based on a fixed number of quantization bits. Simulation results show that the proposed adaptive quantization can reduce the number of quantization bits without error performance degradation.
In this paper, we propose a novel min-sum (MS) decoder architecture using nonuniform quantization schemes for low-density parity-check (LDPC) codes. The finite word-length analysis in implementing an LDPC decoder is a very important factor since it directly impacts the size of memory to store the intrinsic and extrinsic messages and the overall hardware area in the partially parallel LDPC decoder. The proposed nonuniform quantization scheme can reduce the finite word-length while achieving similar performances compared to a conventional quantization scheme. From simulation results, it is shown that the proposed 4-bits nonuniform quantization scheme achieves an acceptable decoding performance unlike a conventional 4-bits uniform quantization scheme. In addition, the hardware implementation for the proposed nonuniform quantization scheme requires smaller area.
在介绍LDPC码概念和基于洪水消息传递机制和积译码算法的基础上,引入基于串行消息传递机制的LDPC译码算法.该串行译码算法可基于校验节点或变量节点一定的顺序进行消息处理和传递,保证更新的消息能够快速进入迭代过程,从而改善消息传递的收敛特性;同时充分利用消息间相互关联的特点,融合消息传递步骤,可以降低所需的存储容量.分析了两种串行译码算法的算法复杂度,证明基于校验节点的串行译码算法能在很大程度上简化译码复杂度,并对比洪水译码算法,在AWGN信道下进行了性能仿真,仿真结果表明两种串行译码算法都使译码性能得到明显提高.
In this paper, we propose an improvement of the normalized min-sum (MS) decoding algorithm and novel MS decoder architectures with reduced word length using nonuniform quantization schemes for low-density parity-check (LDPC) codes. The proposed normalized MS algorithm introduces a more exact adjustment with two optimized correction factors for check-node-updating computations, while the conventional normalized MS algorithm applies only one correction factor. The proposed algorithm provides a significant performance gain without any additional computation or hardware complexity. The finite word-length analysis in implementing an LDPC decoder is a very important factor since it directly impacts the size of memory to store the intrinsic and extrinsic messages and the overall hardware area in the partially parallel LDPC decoder. The proposed nonuniform quantization scheme can reduce the finite word length while achieving similar performances compared to a conventional quantization scheme. From simulation results, it is shown that the proposed 4-bit nonuniform quantization scheme achieves an acceptable decoding performance, unlike the conventional 4-bit uniform quantization scheme. Finally, the proposed MS decoder architectures by the nonuniform quantization scheme provide significant reductions of 20% and up to 8% for the memory area and combinational logic area, respectively, compared to the conventional 5-bit ones.