Qubit readout, or qubit state discrimination, remains one of the slowest and most error-prone operations in superconducting quantum processors, making fast, accurate, and hardware-efficient classification essential for scalable quantum computing. Conventional discriminators integrate the I/Q record into a single point, discarding evidence a relaxing qubit leaves behind; full-resolution feed-forward classifiers recover it but are too costly to deploy under this constraint. Recurrent classifiers retain full resolution far more cheaply, but their loop-carried hidden state cannot fit a single AI Engine (AIE) tile's register capacity and spills to data memory, adding latency that grows with sequence length. We present a hardware-aware LSTM accelerator for an AMD Versal device that resolves this by partitioning at the dependency boundary - independent input projections on the AIE array, the loop-carried update in programmable logic (PL) - keeping pace with a 64 ns input cadence under a 1,000 ns budget. On the qubit affected by mid-readout state transitions, our design matches a full-resolution feed-forward network's accuracy (96.59% vs. 96.37%) using 403x fewer parameters and roughly 103x fewer DSPs while cutting relative error by 68.2% over GMM, 43.6% over QubiCML, and 16.82% over MF-NN. Using 4 out of 400 AIE tiles and 17 DSP58, it needs 2.2-8.2x fewer DSP58 blocks than QubiCML and MF-NN, and the AIE-PL partition cuts exposed tail latency by 60.3% versus a pure-AIE mapping and DSP58 usage 31.1x versus an all-PL implementation. Across eight qubits, a compact variant reaches 96.78% mean accuracy, the strongest hardware-deployed operating point. Temporal resolution and recurrent-state placement must then be treated jointly when designing low-latency quantum readout accelerators.
Qubit readout, or qubit state discrimination, remains one of the slowest and most error-prone operations in superconducting quantum processors, making fast, accurate, and hardware-efficient classification essential for scalable quantum computing. Conventional discriminators integrate the I/Q record into a single point, discarding evidence a relaxing qubit leaves behind; full-resolution feed-forward classifiers recover it but are too costly to deploy under this constraint. Recurrent classifiers retain full resolution far more cheaply, but their loop-carried hidden state cannot fit a single AI Engine (AIE) tile's register capacity and spills to data memory, adding latency that grows with sequence length. We present a hardware-aware LSTM accelerator for an AMD Versal device that resolves this by partitioning at the dependency boundary - independent input projections on the AIE array, the loop-carried update in programmable logic (PL) - keeping pace with a 64 ns input cadence under a 1,000 ns budget. On the qubit affected by mid-readout state transitions, our design matches a full-resolution feed-forward network's accuracy (96.59% vs. 96.37%) using 403x fewer parameters and roughly 103x fewer DSPs while cutting relative error by 68.2% over GMM, 43.6% over QubiCML, and 16.82% over MF-NN. Using 4 out of 400 AIE tiles and 17 DSP58, it needs 2.2-8.2x fewer DSP58 blocks than QubiCML and MF-NN, and the AIE-PL partition cuts exposed tail latency by 60.3% versus a pure-AIE mapping and DSP58 usage 31.1x versus an all-PL implementation. Across eight qubits, a compact variant reaches 96.78% mean accuracy, the strongest hardware-deployed operating point. Temporal resolution and recurrent-state placement must then be treated jointly when designing low-latency quantum readout accelerators.
This work presents QubiCML, a novel FPGA-based system engineered for real-time, in-situ discrimination of two- and three-level quantum states (quitrits) in superconducting quantum processors. Accurate and low-latency identification of quantum states is a critical enabler for scaling quantum computing, particularly as higher-dimensional systems such as qutrits are explored to increase information density, circuit depth, and gate expressivity. QubiCML integrates a lightweight, multi-layer neural network directly into FPGA hardware to classify the qutrit states∣g⟩,∣e⟩, and∣f⟩with high fidelity and minimal latency. Traditional state discrimination methods rely on offline post-processing, resulting in delays incompatible with the short coherence times of superconducting qubits. QubiCML overcomes this bottleneck by performing all inference operations within the FPGA fabric itself, achieving full quantum state discrimination within 66 ns (with softmax) or 40 ns (without softmax). The system supports fast reconfiguration via BRAM-stored parameters, enabling compatibility with varying quantum hardware and dynamic calibration environments. Additionally, we propose FPGA-friendly techniques for data normalization and fixed-point quantization to eliminate the overhead of floating-point and division operations—further optimizing the architecture for real-time deployment. We evaluate QubiCML on in-house superconducting hardware across multiple qubits and qutrits. The system achieves up to 97 % average accuracy for qutrits and up to 99 % for two-level systems, using readout windows as short as 650-750 ns. These results establish QubiCML as one of the first practical implementations of real-time qutrit state discrimination, marking an essential step toward mid-circuit measurements, dynamic feedback, and advanced error correction in higher-dimensional quantum computing.
Accurate and timely quantum state discrimination is critical for quantum computing, particularly in protocols requiring mid-circuit measurement (MCM) and conditional feed-forward. While classical state readout in transistors is near-instantaneous, identifying the state of superconducting qubits remains latency-limited and error-prone. Existing approaches rely on post-processing measurement data transferred to host computers, introducing delays on the order of milliseconds -- vastly exceeding the coherence time of quantum states, which typically last only hundreds of microseconds. To bridge this latency gap, we present an in-situ machine learning (ML) inference engine implemented on a field-programmable gate array (FPGA), enabling real-time quantum state discrimination within 40 ns. Our system supports both two-level (qubit) and three-level (qutrit) systems and performs inference directly on digitized readout signals without host-side intervention. This low-latency operation facilitates mid-circuit measurements, where qubit states are measured and reused within a single quantum circuit, and enables real-time conditional operations essential for quantum error correction. Crucially, fast and accurate mid-circuit readout is a prerequisite for implementing practical fault-tolerant error correction, where errors must be detected and corrected within a single circuit cycle to preserve logical state coherence. We validate our system using superconducting transmon devices, demonstrating robust discrimination fidelity across multiple qubit and qutrit channels. Further, we implement a conditional qutrit logic protocol based on FPGA-resident state classification, highlighting the practical benefits of our approach for NISQ-era quantum algorithms and scalable fault-tolerant architectures.
Identifying the state of a quantum bit (qubit), known as quantum state discrimination, is a crucial operation in quantum computing. However, it has been the most error-prone and time-consuming operation on superconducting quantum processors. Due to stringent timing constraints and algorithmic complexity, most qubit state discrimination methods are executed offline. In this work, we present an enhanced real-time quantum state discrimination system leveraging FPGA-based AI Engine technology. A multi-layer neural network has been developed and implemented on the AMD Xilinx VCK190 FPGA platform, enabling accurate in-situ state discrimination and supporting mid-circuit measurement experiments for multiple qubits. Our approach leverages recent advancements in architecture research and design, utilizing specialized AI/ML accelerators to optimize quantum experiments and reduce the use of FPGA resources.
Measuring a qubit state is a fundamental but error-prone task in quantum computing. As the number of qubits increases, scalable readout demands multiplexed qubit measurement, which often suffers from crosstalk and other nonidealities. The conventional approach of qubit state detection often struggles with scalability and noise resilience. Neural network (NN)-based discriminators have emerged as a promising alternative, offering superior performance for inferring qubit states from multiplexed signals. However, their deployment on hardware platforms like Field programmable gate arrays (FPGA) is hindered by computation complexity, resource constraints, and latency. In this work, we present an end-to-end methodology for designing and deploying quantized NN-based multi-qubit state discriminators on FPGAs. We demonstrate that implementing a fully connected neural network accelerator for multi-qubit readout is advantageous, balancing computational complexity with low latency requirements without significant loss in accuracy. We significantly reduce the FPGA footprint and latency of the neural network by employing quantization-aware training (QAT) to quantize weights, activations, and inputs, and leveraging automated mapping flows for efficient, hardware-aware design-space exploration and optimization. The hardware accelerator performs frequency-multiplexed readout of five superconducting qubits in 26.7 ns, on a radio frequency system on chip (RFSoC) ZCU111 FPGA. These modules can be implemented and integrated into existing FPGA based quantum control and readout platforms, making them ready for experimental deployment.
Fast and accurate qubit-state assignment is essential for feedback, calibration, and error correction in quantum processors. In superconducting platforms, frequency-multiplexed readout makes this task intrinsically multivariate as measured traces can encode crosstalk, qubit-state relaxation events, and other transient nonidealities that are not fully captured by conventional matched filtering. Here, we introduce spiking neural network (SNN) discriminators for superconducting qubit readout. By processing the measurement window in successive time chunks, the networks exploit temporal structure and update classification scores as data arrive, rather than waiting until the end of the readout window. The spiking networks outperform matched-filter discrimination and approach the accuracy of a full-trace artificial neural network. Beyond reaching the performance of artificial neural networks, the key advantage of SNNs is that they provide a streaming, time-resolved estimate of the qubit state that evolves as the readout signal is acquired. Using quantisation-aware training and hls4ml synthesis, we further demonstrate that each FPGA inference update can be completed before the next readout chunk arrives. These results establish spiking neural networks as a promising route to low-latency, real-time qubit readout on FPGA hardware, with broader implications for time-critical quantum-control and scientific-inference applications.
This work addresses the critical challenge of accurately and swiftly identifying quantum states in superconducting quantum processors, with a particular focus on qubit (two-level) states. It introduces QubiCML, an innovative FPGA-based system designed for in-situ, real-time quantum state discrim-ination, which is essential for mid-circuit measurements and the implementation of advanced error correction techniques. By integrating a multi-layer neural network on the FPGA platform, QubiCML achieves exceptional accuracy and low latency in distinguishing quantum states. Traditional methods of quantum state discrimination rely heavily on offline data processing, which is inadequate due to the brief coherence time of quantum states and significant communication delays. QubiCML overcomes these limitations by utilizing in-situ machine learning for state discrimination, enabling real-time state determination in just 54 ns. It optimizes readout RF pulses and digital local oscillator (DLO) signals, significantly enhancing the fidelity of state discrimination. This capability enables mid-circuit measurements (MCM), which we successfully deployed using the QubiCML system. The system has been rigorously evaluated on in-house superconducting quantum processors, demonstrating an impressive average accuracy of 98.5%. QubiCML's modular architecture supports scalability across various qubits, making it adaptable to different quantum computing setups. Its real-time feedback capabilities are particularly beneficial for efficient quantum algorithm development and optimization. This system represents a groundbreaking advance-ment in the field of quantum computing, offering a robust tool for real-time quantum state discrimination. QubiCML has the potential to become the standard method for state discrimination, providing the quantum computing community with a powerful solution to push the boundaries of current technology.