Optimal Scaling of Unitary Design Formation in $U(1)$-Symmetric Random Circuits: A Bottleneck Slower than Charge Transport

Abstract

Understanding randomness formation under conservation laws is important both for characterizing chaotic phenomena in isolated quantum systems and for symmetry-constrained quantum information processing. $U(1)$-symmetric random circuits on an $N$-qubit system provide a minimal tractable setting for this problem, in which the formation rate of unitary designs was conjectured to be governed by charge transport in the underlying circuit geometry. However, whether charge transport indeed sets the slowest relaxation mode has remained an open problem, due to the difficulty in deriving a tight lower bound on the symmetric design formation rate. In this work, we resolve this problem by determining the optimal scaling of the unitary $k$-design formation rate for $k\leq O(\sqrt{\log N})$ across a wide range of circuit geometries, including lattices, expander graphs, and all-to-all interactions. In particular, for $k\geq 2$, we find that the formation rate is governed by a two-particle encounter rate---the rate at which two random walkers encounter each other in a given circuit geometry. This encounter rate is parametrically smaller than the single-particle transport rate in many geometries, thereby disproving the previous conjecture. We further establish that this encounter mechanism indeed sets the design formation rate by deriving its matching lower bound with a novel proof technique based on an auxiliary subgroup ensemble. Although this encounter mode imposes a robust bottleneck on design formation in $U(1)$-symmetric random circuits, we also show that this bottleneck can be circumvented by using symmetry-breaking local gates and provide an explicit protocol that achieves faster design formation. These results establish a new picture of randomness formation under conservation laws and provide guiding principles for characterizing and efficiently generating symmetry-constrained randomness.