Ion trap on borosilicate substrate with integrated femtosecond-laser-written waveguide
Jakob Wahl, Alexander Zesar, Philipp Hurdax, Marco Schmauser, Victoria Schwab, Michael Pasquini, Marco Valentini, Clemens Rössler, Thomas Monz, Bernhard Lamprecht, Klemens Schüppert, Philipp Schindler
quant-phSubmitted Aug 13, 2026• Announced Aug 14, 2026• 0 citations
We present an ion-trap platform on borosilicate glass with an integrated femtosecond-laser-written waveguide for on-chip light delivery. The optical layer is physically separated from the electrode substrate and bonded atop the trap, remaining compatible with silicon-based integration. We engineer single-mode low-loss guidance at 729 nm with tunable mode-field diameter and achieve low-loss curved waveguides down to a radius of curvature of 6 mm. We also extend single-mode operation to a wavelength of 405 nm. The fabrication process is compatible with the industrial fabrication of a single-metal-layer surface-electrode trap, including active fiber alignment and bonding. We validate the platform in a cryogenic trapped-ion system with $^{40}$Ca$^+$, demonstrating trapping, shuttling the ion to a zone in front of the waveguide, and coherent operations driven by 729 nm light delivered through the integrated waveguide. We characterize the effect of the exposed dielectric on the ion and measure stray electric fields that show slow drift at a timescale of hours. The architecture is compatible with hybrid micro-optics (e.g. pick-and-place lenses) to realize single ion addressing and provides a robust, scalable route to integrated light delivery for trapped-ion devices.
We present an ion-trap platform on borosilicate glass with an integrated femtosecond-laser-written waveguide for on-chip light delivery. The optical layer is physically separated from the electrode substrate and bonded atop the trap, remaining compatible with silicon-based integration. We engineer single-mode low-loss guidance at 729 nm with tunable mode-field diameter and achieve low-loss curved waveguides down to a radius of curvature of 6 mm. We also extend single-mode operation to a wavelength of 405 nm. The fabrication process is compatible with the industrial fabrication of a single-metal-layer surface-electrode trap, including active fiber alignment and bonding. We validate the platform in a cryogenic trapped-ion system with 40Ca+, demonstrating trapping, shuttling the ion to a zone in front of the waveguide, and coherent operations driven by 729 nm light delivered through the integrated waveguide. We characterize the effect of the exposed dielectric on the ion and measure stray electric fields that show slow drift at a timescale of hours. The architecture is compatible with hybrid micro-optics (e.g. pick-and-place lenses) to realize single ion addressing and provides a robust, scalable route to integrated light delivery for trapped-ion devices.
Monolithic integration of control technologies for atomic systems presents a promising route to the development of quantum computers and portable quantum sensors. Trapped atomic ions form the basis of high-fidelity quantum information processors and high-accuracy optical clocks, but currently rely on free-space optics for ion control, limiting portability and scalability. Here we demonstrate a surface-electrode ion trap which delivers all wavelengths required for ionization, cooling, coherent operations, and quantum-state preparation and detection of Sr+ qubits using integrated waveguides and grating couplers. Laser light from the violet to the infrared is coupled onto the chip via an optical-fiber array, creating an inherently stable optical path that we use to demonstrate qubit coherence resilient to platform vibrations. This demonstration of CMOS-compatible integrated-photonic surface-trap fabrication, robust packaging, and enhanced qubit coherence represents a key advance in the development of portable trapped-ion quantum sensors and clocks, and it lights the way toward the complete, individual control of larger numbers of ions in quantum information processing systems.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
Abstract Monolithic integration of control technologies for atomic systems is a promising route to the development of quantum computers and portable quantum sensors1–4. Trapped atomic ions form the basis of high-fidelity quantum information processors5, 6 and high-accuracy optical clocks7. However, current implementations rely on free-space optics for ion control, which limits their portability and scalability. Here we demonstrate a surface-electrode ion-trap chip8, 9 using integrated waveguides and grating couplers, which delivers all the wavelengths of light required for ionization, cooling, coherent operations and quantum state preparation and detection of Sr+ qubits. Laser light from violet to infrared is coupled onto the chip via an optical-fibre array, creating an inherently stable optical path, which we use to demonstrate qubit coherence that is resilient to platform vibrations. This demonstration of CMOS-compatible integrated photonic surface-trap fabrication, robust packaging and enhanced qubit coherence is a key advance in the development of portable trapped-ion quantum sensors and clocks, providing a way towards the complete, individual control of larger numbers of ions in quantum information processing systems.
Trapped ions provide a high-fidelity platform for quantum information processing, yet delivery of multiple, distinct wavelengths across large networks of interaction zones remains a bottleneck. Conventional free-space light delivery lacks scalability, while on-chip grating couplers suffer from narrow operational bandwidth that increases circuit footprint and optical interfacing complexity. Here we show a broadband photonic integrated circuit capable of addressing individual ions. The circuit combines a planar waveguide lens with a micromirror fabricated using two-photon polymerization at wafer scale. This implementation can address three individual ions from λ = 405 - 880 nm with -27 dB average intensity crosstalk at 5μm pitch. We trap 40Ca+ and 138Ba+ ions above such devices, characterize optical crosstalk with barium ions, and demonstrate individual repumping of calcium ions. This monolithic photonic architecture brings broadband addressing in an on-chip modality to trapped-ion technology. More generally, integrating additive manufacturing into quantum devices is poised to unlock expanded design space for implementing novel quantum architectures.
In this work, we report ion trap fabrication using prevailing foundry copper back-end-of-line process on a 300mm Si platform. Surface electrodes comprising of ~3.7 µm thick Cu and ~0.2 µm thick of Au surface finish are electroplated above a ~3 µm thick of SiO2 layer on a high-resistivity Si substrate. The innovative process, which is fully compatible with CMOS back-end, enables a fine gap trench structure between the electrodes, such that the exposed dielectric area to the trapped ions is reduced. By optimizing the electroplating process, a relatively flat Cu surface is created with a thin Au layer deposited as an effective protective layer to prevent surface oxidation. The fabricated trap is wire-bonded in a CPGA package for DC and RF testing. Small size Si traps show a good RF dissipation property which is a prerequisite for ion trapping. The further integration of TSV and Si photonics shows a promising prospect in terms of electrical and optical performance enhancement of ion trap.
Integrated optical control of trapped-ion qubits leveraging dielectric waveguides photonics within planar-fabricated trap devices offers routes to scaling the optical control critical to trapped-ion quantum computing. The ultraviolet to infrared functionality required for many atomic systems, the multiple metal layers for large-scale trap arrays, and the long-term interest in integration of active functionality and integrated electronics motivates development of foundry-based platforms for such systems, to facilitate accessibility to the complex fabrication involved. Aside from scaling, utilization of such technology in trapped-ion quantum systems further stands to alleviate limitations on basic physical operations employed in both quantum computing and metrology, which experiments are starting to demonstrate. I will summarize our recent results using phase-stable standing-wave delivery practically enabled by integrated photonic addressing to enhance ground-state laser cooling, which we experimentally demonstrate using trap devices with integrated Al2O3 and Si3N4 waveguides for UV-NIR addressing fabricated in a commercial foundry. I will also discuss relevance of similar ideas to alleviating power requirements in laser-based entangling gates, and work in progress towards experimental realization, including in a 300 mm-wafer foundry platform for such devices in development.