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arXiv:2608.00189

Phase transitions in quantum-circuit compilation

Andrea De Girolamo, Davide Rattacaso, Simone Notarnicola, Ilaria Siloi, Simone Montangero

quant-phcond-mat.stat-mechSubmitted Jul 31, 2026• Announced Aug 4, 2026• 0 citations
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Abstract

Quantum-circuit compilation aims at finding an optimized realization of a target circuit under given constraints, e.g., the minimization of hardware-induced errors and the unitary-equivalence of the circuit. We connect the compilation process with the thermodynamics of a many-body spin system: circuit infidelity plays the role of the energy function and low-temperature states correspond to compiled circuits. In the paradigmatic case where crosstalk between parallel gates is present, we find a phase transition between a disordered phase and an antiferromagnetic brick-wall phase, compatible with the Ising universality class. At larger crosstalk, we observe a $\mathbb{Z}_3$-ordered regime, suggesting that increasingly serial compiled circuits are associated with emergent $\mathbb{Z}_n$-ordered phases. When the unitary-equivalence constraint is removed, these phases disappear, showing that the equivalence between circuits underlies the emergent criticality and constitutes a source of complexity in quantum-circuit compilation and, more generally, in equivalence-constrained optimization. Finally, we observe that the Kolmogorov complexity of the circuit enhances the emergence of ordered phases.

Comments
7+7 pages, 4+5 figures

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Quantum-circuit compilation aims at finding an optimized realization of a target circuit under given constraints, e.g., the minimization of hardware-induced errors and the unitary-equivalence of the circuit. We connect the compilation process with the thermodynamics of a many-body spin system: circuit infidelity plays the role of the energy function and low-temperature states correspond to compiled circuits. In the paradigmatic case where crosstalk between parallel gates is present, we find a phase transition between a disordered phase and an antiferromagnetic brick-wall phase, compatible with the Ising universality class. At larger crosstalk, we observe a Z3\mathbb{Z}_3Z3​-ordered regime, suggesting that increasingly serial compiled circuits are associated with emergent Zn\mathbb{Z}_nZn​-ordered phases. When the unitary-equivalence constraint is removed, these phases disappear, showing that the equivalence between circuits underlies the emergent criticality and constitutes a source of complexity in quantum-circuit compilation and, more generally, in equivalence-constrained optimization. Finally, we observe that the Kolmogorov complexity of the circuit enhances the emergence of ordered phases.
Abstract Quantum noise in real-world devices poses a significant challenge in achieving practical quantum advantage, since accurately compiled and executed circuits are typically deep and highly susceptible to decoherence. To facilitate the implementation of complex quantum algorithms on noisy hardware, we propose an approximate method for compiling target quantum circuits into brick-wall layouts. This new circuit design consists of two-qubit CNOT gates that can be directly implemented on real quantum computers, in conjunction with optimized one-qubit gates, to approximate the essential dynamics of the original circuit while significantly reducing its depth. Our approach is evaluated through numerical simulations of time-evolution circuits for the critical Ising model, quantum Fourier transformation, and Haar-random quantum circuits, as well as experiments on IBM quantum platforms. By accounting for compilation error and circuit noise, we demonstrate that time evolution and quantum Fourier transformation circuits achieve high compression rates, while random quantum circuits are less compressible. The degree of compression is related to the rate of entanglement accumulation in the target circuit. In particular, experiments on IBM platforms achieve a compression rate of 12.512.512.5 for N=12N=12N=12, significantly extending the application of current quantum devices. Furthermore, large-scale numerical simulations for system sizes up to N=30N=30N=30 reveal that the optimal depth dmaxd_{\rm max}dmax​ to achieve maximal overall fidelity is independent of system size NNN, suggesting the scalability of our method for large quantum devices in terms of quantum resources.
Equilibrium learning trains a physical system using observables of its relaxed states. We extend this principle to gate-based quantum circuits by embedding a parametrized circuit in a Feynman-Kitaev (FK) Hamiltonian and imposing the compilation target either through an output clamping term or through a target-dependent cyclic condition on the clock register. The ground state energies and the overlaps of the corresponding ground states with the free history state define faithful cost functions for unitary and state compilation. We show that these costs are nonlinear functions of the compilation infidelity and therefore reshape the optimization landscape. We show that starting from the free history state, quantum phase estimation can prepare the relevant ground states and estimate the cost functions with polynomial resources. In two-qubit benchmarks, optimization with the equilibrium cost functions reaches a fixed fidelity threshold in fewer sweeps than standard compilation infidelity cost function for many instances. The results demonstrate the potential for encoding quantum learning problems as computation of equilibrium observables.
Quantum circuit compilation is a critical step in realizing quantum algorithms on real quantum hardware. Traditional compilation methods often employ static optimization strategies, neglecting the unique constraints and characteristics of the target quantum device. This paper introduces a novel adaptive quantum circuit compilation framework designed to dynamically adjust circuit designs based on hardware-specific information, aiming to minimize gate count and, consequently, error rates. The core of the framework lies in integrating a hardware simulator directly within the compilation process. This allows the compiler to evaluate the performance of various circuit designs—considering factors like qubit connectivity, gate fidelity, and decoherence models—before committing to a final layout. The proposed approach represents a shift from static to adaptive optimization, providing a more nuanced and effective strategy for translating quantum algorithms into executable code on diverse quantum hardware platforms. This research demonstrates a significant potential improvement in quantum circuit efficiency and fidelity, addressing a key bottleneck in the advancement of quantum computing.
Abstract To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.
Realizing a conceptual quantum algorithm on an actual physical device necessitates the algorithm's quantum circuit description to undergo certain transformations in order to adhere to all constraints imposed by the hardware. In this regard, the individual high-level circuit components are first synthesized to the supported low-level gate-set of the quantum computer, before being mapped to the target's architecture-utilizing several optimizations in order to improve the compilation result. Specialized tools for this complex task exist, e.g., IBM's Qiskit, Google's Cirq, Microsoft's QDK, or Rigetti's Forest. However, to date, the circuits resulting from these tools are hardly verified, which is mainly due to the immense complexity of checking if two quantum circuits indeed realize the same functionality. In this paper, we propose an efficient scheme for quantum circuit equivalence checking-specialized for verifying results of the IBM Qiskit quantum circuit compilation flow. To this end, we combine characteristics unique to quantum computing, e.g., its inherent reversibility, and certain knowledge about the compilation flow into a dedicated equivalence checking strategy. Experimental evaluations confirm that the proposed scheme allows to verify even large circuit instances with tens of thousands of operations within seconds or even less, whereas state-of-the-art techniques frequently time-out or require substantially more runtime. A corresponding open source implementation of the proposed method is publicly available at https://github.com/iic-jku/qcec.
Existing quantum systems provide very limited physical qubit counts, trying to execute a quantum algorithm/circuit on them that have a higher number of logical qubits than physically available lead to a compile-time error. Given that it is unrealistic to expect existing quantum systems to provide, in near future, sufficient number of qubits that can accommodate large circuit, there is a pressing need to explore strategies that can somehow execute large circuits on small systems. In this paper, first, we perform an analysis to identify the qubits that are most suitable for circuit resizing. Our results reveal that, in most quantum programs, there exist qubits that can be reused mid-program to serially/sequentially execute the circuit employing fewer qubits. Motivated by this observation, we design, implement and evaluate a compiler-based approach that i) identifies the qubits that can be most beneficial for serial circuit execution; ii) selects those qubits to reuse at each step of execution for size minimization of the circuit; and iii) minimizes Middle Measurement (MM) delays due to impractical implementation of shots to improve the circuit reliability. Furthermore, since our approach intends to execute the circuits sequentially, the crosstalk errors can also be optimized as a result of the reduced number of concurrent gates. The experimental results indicate that our proposed approach can (i) execute large circuits that initially cannot fit into small circuits, on small quantum hardware, and (ii) can significantly improve the PST of the results by 2.1X when both original and our serialized programs can fit into the target quantum hardware.