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arXiv:2604.15432

Efficient nnn-qubit entangling operations via a superconducting quantum router

Xuntao Wu, Haoxiong Yan, Gustav Andersson, Alexander Anferov, Christopher R. Conner, Yash J. Joshi, Bayan Karimi, Amber M. King, Shiheng Li, Howard L. Malc, Jacob M. Miller, Harsh Mishra, Hong Qiao, Minseok Ryu, Jian Shi, Andrew N. Cleland

quant-phSubmitted Apr 16, 2026• Announced Apr 20, 2026• 0 citations
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Abstract

Quantum algorithms on near-term quantum processors are typically executed using shallow quantum circuits composed of one- and two-qubit gates. However, as circuit depth and gate number increase, gate imperfections and qubit decoherence begin to dominate, limiting algorithmic complexity. An alternative approach is to explore gates involving more than two qubits. In previous work (X. Wu et al., Physical Review X 14, 041030 (2024)), we demonstrated a new superconducting qubit architecture with user-selectable two-qubit interactions via a reconfigurable router, used to connect pairs of qubits. Here, we leverage this novel architecture to realize programmable and efficient multi-qubit operations involving more than two qubits, resulting in faster preparation of multi-qubit entangled states with good fidelities. We also successfully apply model-free reinforcement learning to perform multi-qubit gates, including training a two-qubit controlled-Z gate as well as three-qubit controlled-SWAP and controlled-controlled-phase (Fredkin and Toffoli) gates. Higher $n$th-order gates may also be feasible, using our high-connectivity router design. This could provide a more efficient and higher-fidelity implementation of complex quantum algorithms and a more practical approach to quantum computation.

Comments
29 pages, 12 figures

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Quantum algorithms on near-term quantum processors are typically executed using shallow quantum circuits composed of one- and two-qubit gates. However, as circuit depth and gate number increase, gate imperfections and qubit decoherence begin to dominate, limiting algorithmic complexity. An alternative approach is to explore gates involving more than two qubits. In previous work (X. Wu et al., Physical Review X 14, 041030 (2024)), we demonstrated a new superconducting qubit architecture with user-selectable two-qubit interactions via a reconfigurable router, used to connect pairs of qubits. Here, we leverage this novel architecture to realize programmable and efficient multi-qubit operations involving more than two qubits, resulting in faster preparation of multi-qubit entangled states with good fidelities. We also successfully apply model-free reinforcement learning to perform multi-qubit gates, including training a two-qubit controlled-Z gate as well as three-qubit controlled-SWAP and controlled-controlled-phase (Fredkin and Toffoli) gates. Higher nnnth-order gates may also be feasible, using our high-connectivity router design. This could provide a more efficient and higher-fidelity implementation of complex quantum algorithms and a more practical approach to quantum computation.
Superconducting qubits provide a promising approach to large-scale fault-tolerant quantum computing. However, qubit connectivity on a planar surface is typically restricted to only a few neighboring qubits. Achieving longer-range and more flexible connectivity, which is particularly appealing in light of recent developments in error-correcting codes, however, usually involves complex multilayer packaging and external cabling, which is resource intensive and can impose fidelity limitations. Here, we propose and realize a high-speed on-chip quantum processor that supports reconfigurable all-to-all coupling with a large on-off ratio. We implement the design in a four-node quantum processor, built with a modular design comprising a wiring substrate coupled to two separate qubit-bearing substrates, each including two single-qubit nodes. We use this device to demonstrate reconfigurable controlled- Z gates across all qubit pairs, with a benchmarked average fidelity of 96.00 % ± 0.08 % and best fidelity of 97.14 % ± 0.07 % , limited mainly by dephasing in the qubits. We also generate multiqubit entanglement, distributed across the separate modules, demonstrating GHZ-3 and GHZ-4 states with fidelities of 88.15 % ± 0.24 % and 75.18 % ± 0.11 % , respectively. This approach promises efficient scaling to larger-scale quantum circuits and offers a pathway for implementing quantum algorithms and error-correction schemes that benefit from enhanced qubit connectivity. Published by the American Physical Society 2024
Scaling superconducting quantum processors requires interconnects that provide both non-local connectivity and parallel entangling operations. While current quantum routers offer greater connectivity than nearest-neighbour topologies, their support for parallel, independently addressable two-qubit gates remains fundamentally limited, imposing severe compilation overheads that constitute a critical bottleneck. Here we introduce a bus-based reconfigurable quantum router that enables parallel controlled-ZZZ (CZ) gates for modular superconducting processors. Constructed from a flux-tunable SQUID network, the router selectively connects interface qubits to two shared buses, allowing destructive interference to suppress idle interactions while supporting two disjoint CZ gates in parallel. Full-system Hamiltonian simulations yield parallel-gate infidelities ranging from 7.9×10−47.9\times10^{-4}7.9×10−4 to 1.8×10−31.8\times10^{-3}1.8×10−3 under the operating conditions considered, and an open-system analysis identifies the coherence requirements for high-fidelity operation. We further assess the circuit-level consequences using hardware-aware compilation and resource-constrained scheduling. For the 36-qubit quantum Fourier transform (QFT), QAOA-MaxCut, and random-pairing circuits, the router reduces the median SWAP count by up to 34%34\%34% and the native CZ count by up to 20%20\%20% relative to a matched two-dimensional grid. Circuit-depth reductions are workload-dependent, reaching 20%20\%20% for QAOA-MaxCut but remaining negligible for the QFT despite its lower gate count. These results show that enhanced connectivity and schedulable parallelism provide complementary benefits for connectivity-intensive algorithms, establishing the router as a compiler-visible hardware resource and providing a scalable architectural pathway toward constructing highly connected modular superconducting quantum processors.
While the common practice of decomposing general quantum algorithms into a collection of single- and two-qubit gates is conceptually simple, in many cases it is possible to have more efficient solutions where quantum gates engaging multiple qubits are used. In the noisy intermediate-scale quantum (NISQ) era where a universal error correction is still unavailable, this strategy is particularly appealing since it can significantly reduce the computational resources required for executing quantum algorithms. In this work, we experimentally investigate a three-qubit Controlled-CPHASE-SWAP (CCZS) gate on superconducting quantum circuits. By exploiting the higher energy levels of superconducting qubits, we are able to realize a Fredkin-like CCZS gate with a duration of 40 ns, which is comparable to typical single- and two-qubit gates realized on the same platform. By performing quantum process tomography for the two target qubits, we obtain a process fidelity of 86.0% and 81.1% for the control qubit being prepared in ∣0〉 and ∣1〉, respectively. We also show that our scheme can be readily extended to realize a general CCZS gate with an arbitrary swap angle. The results reported here provide valuable additions to the toolbox for achieving large-scale hardware-efficient quantum circuits.
The set of quantum logic gates that can be easily implemented is fundamental to the performance of quantum computers, as it governs the accuracy of basic quantum operations and dictates the complexity of implementing quantum algorithms. Traditional approaches to extending gate sets often require operating devices outside the ideal parameter regimes used to realize qubits, leading to increased control complexity while offering only a limited set of gates. Here we experimentally demonstrate a unified and versatile gate scheme capable of generating arbitrary two-qubit gates using only an exchange interaction and qubit driving on a superconducting quantum processor. We achieve high fidelities averaging 99.38% across a wide range of commonly used two-qubit unitaries, enabling precise multipartite entangled state preparation. Furthermore, we successfully produce a B gate, which efficiently synthesizes the entire family of two-qubit gates. Our results establish that fully exploiting the capabilities of the exchange interaction can yield a comprehensive and highly accurate gate set. With maximum expressivity, optimal gate time, demonstrated high fidelity and easy adaption to other quantum platforms, our unified control scheme offers the prospect of improved performance in quantum hardware and algorithm development. The efficiency of a quantum computer depends on which basic operations it can implement. Now a scheme that can implement any two-qubit logic gate has been demonstrated on a superconducting architecture.
Abstract While all quantum algorithms can be expressed in terms of single-qubit and two-qubit gates, more expressive gate sets can help reduce the algorithmic depth. This is important in the presence of gate errors, especially those due to decoherence. Using superconducting qubits, we have implemented a three-qubit gate by simultaneously applying two-qubit operations, thereby realizing a three-body interaction. This method straightforwardly extends to other quantum hardware architectures, requires only a firmware upgrade to implement, and is faster than its constituent two-qubit gates. The three-qubit gate represents an entire family of operations, creating flexibility in the quantum-circuit compilation. We demonstrate a process fidelity of 97.90%, which is near the coherence limit of our device. We then generate two classes of entangled states, the Greenberger–Horne–Zeilinger and Dicke states, by applying the new gate only once; in comparison, decompositions into the standard gate set would have a two-qubit gate depth of two and three, respectively. Finally, we combine characterization methods and analyze the experimental and statistical errors in the fidelity of the gates and of the target states.
Limited qubit connectivity is a central architectural constraint in superconducting quantum processors, whose planar layouts require additional gates to mediate interactions between distant qubits. Here, we use the AshN control scheme, where rich two-qubit control on every nearest-neighbour pair allows a logical interaction and the required qubit routing to be merged into a single native operation, effectively transforming a sparse hardware graph into a more connected computational architecture. For the benchmark instances studied, the resulting synthesis capability enables reliable execution on constrained one- and two-dimensional lattices, with compiled two-qubit gate counts approaching those of an all-to-all-connected reference. Across seven benchmark circuits on one- and two-dimensional topologies, the AshN-based implementation achieves geometric-mean reductions of 45.2%45.2\%45.2% and 43.7%43.7\%43.7% in two-qubit gate count compared with controlled-Z-based compilation, respectively. Using AshN gates, we prepare an eight-qubit two-excitation Dicke state with a fidelity of 0.7360.7360.736 and certify its genuine multipartite entanglement using a fully positive-partial-transpose witness, whereas the same witness does not certify entanglement for the CZ-based implementation. The state fidelity and entanglement certification remain robust across the tested lattice configurations, including those with up to three connectivity defects. Our work establishes native-gate engineering as a practical approach to mitigating connectivity constraints.