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arXiv:2603.00625

Closing the Loop: Resource-aware Hybrid NAS Guided by Analytical and Hardware-Calibrated Quantum Cost Modeling

Muhammad Kashif, Alberto Marchisio, Muhammad Shafique

quant-phSubmitted Feb 28, 2026• Announced Mar 3, 2026• 0 citations
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Abstract

Hybrid quantum-classical neural networks (HQNNs) integrate quantum circuits with classical layers, each operating under fundamentally different computational paradigms, which makes hardware resource estimation challenging. The training of quantum circuits on real devices requires thousands of circuit executions, which is impractical on current NISQ devices. Therefore, most HQNNs are evaluated on classical simulators, with hardware cost approximated using floating-point operations (FLOPs). However, FLOPs and existing quantum resource estimation methods (e.g., gate counts) overlook key quantum hardware-specific factors such as gate durations, limited qubit connectivity, and noise, all of which ultimately determine the true cost and scalability of quantum circuits. In this paper, we propose an analytical quantum cost model that estimates quantum hardware resources using real backend calibration data, incorporating gate durations, routing overheads, and noise-induced sampling inefficiencies. To complement this, we develop a classical cost model that converts FLOPs into device-specific throughput, enabling a unified time-based representation of hardware resource cost for both subsystems of HQNNs. Building on these analytical models, we present Hyb-HANAS, a hardware-aware hybrid neural architecture search framework, which jointly optimizes accuracy, hardware cost, and parameter count using NSGA-II. Hyb-HANAS identifies Pareto-optimal trade-offs and cross-domain co-adaptation between classical and quantum components of HQNNs. Beyond NAS, the proposed analytical quantum cost model is broadly applicable to quantum hardware benchmarking, compiler evaluation, and training-time estimation of quantum circuits on NISQ devices.

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Accepted at 63rd Design Automation Conference (DAC), Long Beach, CA, USA, July 2026

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Hybrid quantum-classical neural networks (HQNNs) integrate quantum circuits with classical layers, each operating under fundamentally different computational paradigms, which makes hardware resource estimation challenging. The training of quantum circuits on real devices requires thousands of circuit executions, which is impractical on current NISQ devices. Therefore, most HQNNs are evaluated on classical simulators, with hardware cost approximated using floating-point operations (FLOPs). However, FLOPs and existing quantum resource estimation methods (e.g., gate counts) overlook key quantum hardware-specific factors such as gate durations, limited qubit connectivity, and noise, all of which ultimately determine the true cost and scalability of quantum circuits.
In this paper, we propose an analytical quantum cost model that estimates quantum hardware resources using real backend calibration data, incorporating gate durations, routing overheads, and noise-induced sampling inefficiencies. To complement this, we develop a classical cost model that converts FLOPs into device-specific throughput, enabling a unified time-based representation of hardware resource cost for both subsystems of HQNNs. Building on these analytical models, we present Hyb-HANAS, a hardware-aware hybrid neural architecture search framework, which jointly optimizes accuracy, hardware cost, and parameter count using NSGA-II. Hyb-HANAS identifies Pareto-optimal trade-offs and cross-domain co-adaptation between classical and quantum components of HQNNs. Beyond NAS, the proposed analytical quantum cost model is broadly applicable to quantum hardware benchmarking, compiler evaluation, and training-time estimation of quantum circuits on NISQ devices.
Hybrid quantum-classical neural networks (HQNNs) integrate quantum circuits with classical layers, each operating under fundamentally different computational paradigm, which makes hardware-resource estimation challenging. Also, the training of quantum circuits on real devices requires thousands of circuit executions, which is impractical on current NISQ devices. Therefore, most HQNNs are evaluated on classical simulators, with hardware cost approximated using floating-point operations (FLOPs). However, FLOPs and existing quantum resource estimation methods (e.g., gate counts) overlook key quantum hardware-specific factors such as gate durations, limited qubit connectivity, and noise, all of which ultimately determine the true cost and scalability of quantum circuits.
Hybrid quantum-classical neural networks (HQNNs) are emerging as a practical approach for quantum machine learning in the noisy intermediate-scale quantum (NISQ) era, as they combine classical learning components with parameterized quantum circuits in an end-to-end trainable framework. However, their performance and efficiency depend strongly on architectural choices such as data encoding, circuit structure, measurement design, and the coupling between classical and quantum modules. This makes manual design increasingly difficult, especially when hardware limitations and resource constraints must also be taken into account. In this paper, we study the foundations of HQNNs and neural architecture search (NAS), discuss how NAS extends to quantum and hybrid settings, and demonstrate FLOPs-aware search (where FLOPs serve as a proxy for computational complexity), as an important hardware-aware direction for building HQNNs that are not only accurate but also computationally efficient and practically deployable.
Hybrid Quantum Neural Networks (HQNNs), which combine parameterized quantum circuits with classical neural layers, are emerging as promising models in the noisy intermediate-scale quantum (NISQ) era. While quantum circuits are not naturally measured in floating point operations (FLOPs), most HQNNs (in NISQ era) are still trained on classical simulators where FLOPs directly dictate runtime and scalability. Hence, FLOPs represent a practical and viable metric to measure the computational complexity of HQNNs. In this work, we introduce FAQNAS, a FLOPs-aware neural architecture search (NAS) framework that formulates HQNN design as a multi-objective optimization problem balancing accuracy and FLOPs. Unlike traditional approaches, FAQNAS explicitly incorporates FLOPs into the optimization objective, enabling the discovery of architectures that achieve strong performance while minimizing computational cost. Experiments on five benchmark datasets (MNIST, Digits, Wine, Breast Cancer, and Iris) show that quantum FLOPs dominate accuracy improvements, while classical FLOPs remain largely fixed. Pareto-optimal solutions reveal that competitive accuracy can often be achieved with significantly reduced computational cost compared to FLOPs-agnostic baselines. Our results establish FLOPs-awareness as a practical criterion for HQNN design in the NISQ era and as a scalable principle for future HQNN systems.
Designing quantum neural networks (QNNs) that are both accurate and deployable on NISQ hardware is challenging. Handcrafted ansatze must balance expressivity, trainability, and resource use, while limited qubits often necessitate circuit cutting. Existing quantum architecture search methods primarily optimize accuracy while only heuristically controlling quantum and mostly ignore the exponential overhead of circuit cutting. We introduce QNAS, a neural architecture search framework that unifies hardware aware evaluation, multi objective optimization, and cutting overhead awareness for hybrid quantum classical neural networks (HQNNs). QNAS trains a shared parameter SuperCircuit and uses NSGA-II to optimize three objectives jointly: (i) validation error, (ii) a runtime cost proxy measuring wall clock evaluation time, and (iii) the estimated number of subcircuits under a target qubit budget. QNAS evaluates candidate HQNNs under a few epochs of training and discovers clear Pareto fronts that reveal tradeoffs between accuracy, efficiency, and cutting overhead. Across MNIST, Fashion-MNIST, and Iris benchmarks, we observe that embedding type and CNOT mode selection significantly impact both accuracy and efficiency, with angle-y embedding and sparse entangling patterns outperforming other configurations on image datasets, and amplitude embedding excelling on tabular data (Iris). On MNIST, the best architecture achieves 97.16% test accuracy with a compact 8 qubit, 2 layer circuit; on the more challenging Fashion-MNIST, 87.38% with a 5 qubit, 2 layer circuit; and on Iris, 100% validation accuracy with a 4 qubit, 2 layer circuit. QNAS surfaces these design insights automatically during search, guiding practitioners toward architectures that balance accuracy, resource efficiency, and practical deployability on current hardware.
Deploying quantum machine learning algorithms on near-term quantum hardware requires circuits that respect device-specific gate sets, connectivity constraints, and noise characteristics. We present a hardware-aware Neural Architecture Search (NAS) approach for designing quantum feature maps that are natively executable on IBM quantum processors without transpilation overhead. Using genetic algorithms to evolve circuit architectures constrained to IBM Torino native gates (ECR, RZ, SX, X), we demonstrate that automated architecture search can discover quantum Support Vector Machine (QSVM) feature maps achieving competitive performance while guaranteeing hardware compatibility. Evaluated on the UCI Breast Cancer Wisconsin dataset, our hardware-aware NAS discovers a 12-gate circuit using exclusively IBM native gates (6 ECR, 3 SX, 3 RZ) that achieves 91.23 % accuracy on 10 qubits-matching unconstrained gate search while requiring zero transpilation. This represents a 27 percentage point improvement over hand-crafted quantum feature maps (64 % accuracy) and approaches the classical RBF SVM baseline (93 %). We show that removing architectural constraints (fixed RZ placement) within hardware-aware search yields 3.5 percentage point gains, and that 100 % native gate usage eliminates decomposition errors that plague universal gate compilations. Our work demonstrates that hardware-aware NAS makes quantum kernel methods practically deployable on current noisy intermediate-scale quantum (NISQ) devices, with circuit architectures ready for immediate execution without modification.
Hybrid Quantum Neural Networks (HQNNs), under the umbrella of Quantum Machine Learning (QML), have garnered significant attention due to their potential to enhance computational performance by integrating quantum layers within traditional neural network (NN) architectures. Despite numerous state-of-the-art applications, a fundamental question remains: Does the inclusion of quantum layers offer any computational advantage over purely classical models? If yes/no, how and why? In this paper, we analyze how classical and hybrid models adapt their architectural complexity in response to increasing problem complexity. To this end, we select a multiclass classification problem and perform comprehensive benchmarking of classical models for increasing problem complexity, identifying those that optimize both accuracy and computational efficiency to establish a robust baseline for comparison. These baseline models are then systematically compared with HQNNs by evaluating the rate of increase in floating-point operations (FLOPs) and number of parameters, providing insights into how architectural complexity scales with problem complexity in both classical and hybrid networks. We utilize classical machines to simulate the quantum layers in HQNNs, a common practice in Noisy Intermediate-Scale Quantum (NISQ) era. Our analysis reveals that, as problem complexity increases, the architectural complexity of HQNNs, and consequently their FLOPs consumption, despite the simulation overhead associated with quantum layer’s simulation on classical hardware, scales more efficiently (53.1%(53.1 \%(53.1% increase in FLOPs from 10 features (low problem complexity) to 110 features (high problem complexity)), compared to classical networks (88.1%). Moreover, as the problem complexity increases, classical networks consistently exhibit a need for a larger number of parameters to accommodate the increasing problem complexity. Additionally, the rate of increase in number of parameters is also slower in HQNNs (81.4%) than classical NNs (88.5%). These findings suggest that HQNNs provide a more scalable and resource-efficient solution, positioning them as a promising alternative for tackling complex computational problems.