We present a footprint study for the scaling of modular quantum error correction (QEC) protocols designed for triangular color codes, including a lattice-surgery-based logical teleportation gadget, and compare the performance of various possible architectures based on trapped ions. The differences in these architectures arise from the technology that enables the connectivity between physical qubits and the modularity required for the QEC gadgets, which is either based on laser-beam deflectors focused to independent modules hosting mid-size ion crystals, or integrated photonics guided to segmented modules of the trap and allowing for the manipulation of smaller ion crystals. Our approach integrates the transpilation of the QEC gadgets into native trapped-ion primitives and a detailed account of the specific laser addressing and ion transport leading to different amounts of crosstalk errors, motional excitation and idle qubit errors. Combining a microscopically-informed noise model with an efficient Pauli-frame simulator and different scalable decoders, we assess the near-term performance of the color-code memory and teleportation protocols on these architectures. Our analysis demonstrates that modular color-code teleportation is achievable in these near-term trapped-ion architectures, and identifies the integrated-photonics connectivity as the most promising route for longer-term scaling.
We present a footprint study for the scaling of modular quantum error correction (QEC) protocols designed for triangular color codes, including a lattice-surgery-based logical teleportation gadget, and compare the performance of various possible architectures based on trapped ions. The differences in these architectures arise from the technology that enables the connectivity between physical qubits and the modularity required for the QEC gadgets, which is either based on laser-beam deflectors focused to independent modules hosting mid-size ion crystals, or integrated photonics guided to segmented modules of the trap and allowing for the manipulation of smaller ion crystals. Our approach integrates the transpilation of the QEC gadgets into native trapped-ion primitives and a detailed account of the specific laser addressing and ion transport leading to different amounts of crosstalk errors, motional excitation and idle qubit errors. Combining a microscopically-informed noise model with an efficient Pauli-frame simulator and different scalable decoders, we assess the near-term performance of the color-code memory and teleportation protocols on these architectures. Our analysis demonstrates that modular color-code teleportation is achievable in these near-term trapped-ion architectures, and identifies the integrated-photonics connectivity as the most promising route for longer-term scaling.
Active quantum error correction has been identified as a crucial ingredient of future quantum computers, motivating the recent experimental efforts to encode logical quantum bits using small topological codes. In addition to the demonstration of the beneficial role of the encoding, a break-even point in the progress towards large-scale quantum computers will be the implementation of a universal set of gates. This midterm challenge will soon be faced by various quantum technologies, which urges the need of realistic assessments of their prospects. In this work, we pursue this goal by assessing the capability of current trapped-ion architectures in facing one of the most demanding parts of this quest: the implementation of an entangling controlled-NOT (CNOT) gate between encoded logical qubits. We present a detailed comparative study of two alternative strategies for trapped-ion topological color codes, either a transversal or a lattice-surgery approach, characterized by a detailed microscopic modeling of both current technological capabilities and experimental sources of noise afflicting the different operations. Our careful fault-tolerant design, together with a low-resource optimization, allows us to determine via exhaustive numerical simulations the experimental regimes where each of the approaches becomes favorable. We hope that our study thereby contributes to guiding the future development of trapped-ion quantum computers.
In the era of early fault-tolerant quantum computing, basic demonstrations of entanglement operations between a few logical qubits are at the frontier of recent developments in quantum computing. In this work, we describe in detail, at both the logical and physical qubit levels, a logical teleportation protocol between two surface code logical qubits based on lattice surgery. We address several aspects of the teleportation protocol pertinent to superconducting qubit architectures. We explore the modularity constraints in the number and location of stabilizer readouts and compare variants of the teleportation protocol in this regard. Additionally, we investigate potential performance improvements related to in-sequence decision logic and the optimal size of the interface region between two surface code patches on a superconducting chip. Based on our simulations, we show possible near-term improvements in lattice surgery protocols that facilitate fault-tolerant quantum computing in superconducting circuit architectures.
Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.
Modularization promises to break down the design and implementation complexity of large scale quantum processors into smaller manageable subtasks. In this approach, quantum channels, realized for instance through physical rerouting of qubits or quantum teleportation, connect multiple modules. Each of those modules hosts a subset of qubits, e.g. multiple logical qubits, and provides quantum operations on them. In this work, we implement for the first time all logical operations required for modular fault-tolerant universal quantum computing with a non-Calderbank-Shor-Steane (CSS) code, the perfect [[5,1,3]] code, on a trapped-ion quantum computer. This code is the smallest quantum error-correcting (QEC) code capable of correcting any single-qubit error, making it a compact alternative to larger CSS codes. We demonstrate logical state teleportation and a full suite of fault-tolerant operations required for universal logical control, including logical state preparation, QEC with real-time feedback, logical measurements, magic-state preparation, logical entangling operations, and magic-state injection. Moreover, we characterize the logical spectator error picked up by idling logical qubits during quantum operations on distinct qubit registers and demonstrate a logical Pauli quantum process tomography that minimizes required sampling resources for logical tomography.
In order to achieve error rates necessary for advantageous quantum algorithms, Quantum Error Correction (QEC) will need to be employed, improving logical qubit fidelity beyond what can be achieved physically. As today's devices begin to scale, co-designing architectures for QEC with the underlying hardware will be necessary to reduce the daunting overheads and accelerate the realization of practical quantum computing. In this work, we focus on logical computation in QEC. We address quantum computers made from neutral atom arrays to design a surface code architecture that translates the hardware's higher physical connectivity into a higher logical connectivity. We propose groups of interleaved logical qubits, gaining all-to-all connectivity within the group via efficient transversal CNOT gates. Compared to standard lattice surgery operations, this reduces both the overall qubit footprint and execution time, lowering the spacetime overhead needed for small-scale QEC circuits. We also explore the architecture's scalability. We look at using physical atom movement schemes and propose interleaved lattice surgery which allows an all-to-all connectivity between qubits in adjacent interleaved groups, creating a higher connectivity routing space for large-scale circuits. Using numerical simulations, we evaluate the total routing time of interleaved lattice surgery and atom movement for various circuit sizes. We identify a cross-over point defining intermediate-scale circuits where atom movement is best and large-scale circuits where interleaved lattice surgery is best. We use this to motivate a hybrid approach as devices continue to scale, with the choice of operation depending on the routing distance.
Quantum low-density parity check (QLDPC) codes may lead to order-of-magnitude reductions in the qubit overhead required for fault-tolerant quantum computation. Achieving this improved overhead requires logical operations that selectively address individual logical qubits encoded within multi-qubit code blocks. Recently proposed architectures achieve this through QLDPC surgery, in which non-destructive Pauli measurements are performed using ancillary ''gadget'' systems transiently entangled with the code block, generalising lattice surgery. Here we implement QLDPC surgery on a [[10,2,3]] generalised bicycle code using Quantinuum's H2-2 trapped ion processor. A single-round surgery measurement using seven gadget qubits measures the Xˉ1 operator with a 0.72 [0.32, 1.41]% (95% credible interval) error rate and agrees with subsequent transversal measurement with 1.03 [0.60, 1.65]% error. Decoding across three rounds of syndrome extraction suppresses the gadget measurement error, reducing the error rate to below 0.26%. The syndrome after surgery confirms return to the code space and the unaddressed ''spectator'' qubit is preserved with error 0.21 [0.04, 0.67]% during the three-round measurement. We further demonstrate composition of conjugate basis gadgets by sequentially measuring Xˉ1 then Zˉ2, reusing the gadget qubits, and obtain a 1.12 [0.60, 1.94]% error in the Zˉ2 measurement. These results constitute a hardware validation of the generalised surgery primitive underlying Pauli-based computing for QLDPC architectures.