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arXiv:2511.21885

Lattice Surgery Aware Resource Analysis for the Mapping and Scheduling of Quantum Circuits for Scalable Modular Architectures

Batuhan Keskin, Cameron Afradi, Sylvain Lovis, Maurizio Palesi, Pau Escofet, Carmen G. Almudever, Edoardo Charbon

quant-phcs.ETSubmitted Nov 26, 2025• Announced Nov 28, 2025• 0 citations
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Abstract

Quantum computing platforms are evolving to a point where placing high numbers of qubits into a single core comes with certain difficulties such as fidelity, crosstalk, and high power consumption of dense classical electronics. Utilizing distributed cores, each hosting logical data qubits and logical ancillas connected via classical and quantum communication channels, offers a promising alternative. However, building such a system for logical qubits requires additional optimizations, such as minimizing the amount of state transfer between cores for inter-core two-qubit gates and optimizing the routing of magic states distilled in a magic state factory. In this work, we investigate such a system and its statistics in terms of classical and quantum resources. First, we restrict our quantum gate set to a universal gate set consisting of CNOT, H, T, S, and Pauli gates. We then developed a framework that can take any quantum circuit, transpile it to our gate set using Qiskit, and then partition the qubits using the KaHIP graph partitioner to balanced partitions. Afterwards, we built an algorithm to map these graphs onto the 2D mesh of quantum cores by converting the problem into a Quadratic Assignment Problem with Fixed Assignment (QAPFA) to minimize the routing of leftover two-qubit gates between cores and the total travel of magic states from the magic state factory. Following this stage, the gates are scheduled using an algorithm that takes care of the timing of the gate set. As a final stage, our framework reports detailed statistics such as the number of classical communications, the number of EPR pairs and magic states consumed, and timing overheads for pre- and post- processing for inter-core state transfers. These results help to quantify both classical and quantum resources that are used in distributed logical quantum computing architectures.

Comments
20 pages, 15 figures

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•Aug 12, 2026•0 citations
Quantum computing platforms are evolving to a point where placing high numbers of qubits into a single core comes with certain difficulties such as fidelity, crosstalk, and high power consumption of dense classical electronics. Utilizing distributed cores, each hosting logical data qubits and logical ancillas connected via classical and quantum communication channels, offers a promising alternative. However, building such a system for logical qubits requires additional optimizations, such as minimizing the amount of state transfer between cores for inter-core two-qubit gates and optimizing the routing of magic states distilled in a magic state factory. In this work, we investigate such a system and its statistics in terms of classical and quantum resources. First, we restrict our quantum gate set to a universal gate set consisting of CNOT, H, T, S, and Pauli gates. We then developed a framework that can take any quantum circuit, transpile it to our gate set using Qiskit, and then partition the qubits using the KaHIP graph partitioner to balanced partitions. Afterwards, we built an algorithm to map these graphs onto the 2D mesh of quantum cores by converting the problem into a Quadratic Assignment Problem with Fixed Assignment (QAPFA) to minimize the routing of leftover two-qubit gates between cores and the total travel of magic states from the magic state factory. Following this stage, the gates are scheduled using an algorithm that takes care of the timing of the gate set. As a final stage, our framework reports detailed statistics such as the number of classical communications, the number of EPR pairs and magic states consumed, and timing overheads for pre- and post- processing for inter-core state transfers. These results help to quantify both classical and quantum resources that are used in distributed logical quantum computing architectures.
Fault-tolerant quantum processors based on topological codes execute programs through lattice surgery, where operations must be mapped, routed, and supplied with magic states across a 2D grid of physical patches. Non-Clifford operations require these magic states, produced either by distillation factories or by cultivation, each trading footprint against preparation latency, and delivering a magic state to the data patches that consume it requires routing through the same shared layout as every other operation. Yet placement, routing, scheduling, and magic-state supply cannot be optimized in isolation: two operations with no circuit-level dependency can still contend for the same ports, routes, or magic-state terminals once placed, so a compiler that decouples instruction scheduling from magic-state generation, or hard-codes a single generation protocol, is forced to trade execution time against layout footprint instead of co-optimizing both across protocols. We present Harvest, a resource-aware compilation approach for lattice-surgery that co-optimizes magic-state consumption with circuit-aware placement and congestion-aware routing under a protocol-agnostic resource model, then reclaims unused layout footprint after scheduling. Across standard benchmark suites (QAOA, QFT, QASMBench), Harvest achieves an average speedup of 4.83×4.83\times4.83× (up to 17.8×17.8\times17.8×) over sequential execution, improves schedule length by up to 1.35×1.35\times1.35× through circuit-aware placement, and reclaims up to 72.0%72.0\%72.0% of unused magic-state patches and 33.9%33.9\%33.9% of unused routing patches.
Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate.
Abstract To overcome the physical limitations of current quantum hardware in terms of available qubits and connectivity, distributed quantum computing (DQC) has emerged as a promising and scalable paradigm. However, in distributed settings, cross-node qubit interactions incur high communication overhead due to the use of costly quantum communication protocols. Efficient circuit partitioning and transmission cost optimization have thus become key challenges. This work addresses the often-overlooked issues of hardware heterogeneity and redundant transmission by proposing a resource-aware partitioning and transmission cost optimization method for distributed quantum circuits. First, we develop a partitioning framework constrained by qubit resources, which accommodates node capacity differences to enable flexible qubit allocation. Second, we model gate dependencies using a directed acyclic graph (DAG) representation and introduce formal criteria to detect “initial-state” and “final-state” redundancies. A measurement-reset strategy is then employed to replace part of the quantum communication, reducing inter-node data transmission. Experimental results on a variety of benchmark circuits and heterogeneous architectures demonstrate that our method significantly reduces transmission cost and improves overall resource utilization. These findings offer both theoretical insight and practical guidance for efficient distributed quantum computing.
To overcome the physical limitations of scaling monolithic quantum computers, distributed quantum computing (DQC) interconnects multiple smaller-scale quantum processing units (QPUs) to form a quantum network. However, this approach introduces a critical challenge, namely the high cost of quantum communication between remote QPUs incurred by quantum state teleportation and quantum gate teleportation. To minimize this communication overhead, DQC compilers must strategically partition quantum circuits by mapping logical qubits to distributed physical QPUs. Static graph partitioning methods are fundamentally ill-equipped for this task as they ignore execution dynamics and underlying network topology, while metaheuristics require substantial computational runtime. In this work, we propose a heuristic based on beam search to solve the circuit partitioning problem. Our time-aware algorithm incrementally constructs a low-cost sequence of qubit assignments across successive time steps to minimize overall communication overhead. The time and space complexities of the proposed algorithm scale quadratically with the number of qubits and linearly with circuit depth, offering a significant computational speedup over common metaheuristics. We demonstrate that our proposed algorithm consistently achieves significantly lower communication costs than static baselines across varying circuit sizes, depths, and network topologies, providing an efficient compilation tool for near-term distributed quantum hardware.
To address the scalability challenges of quantum computing, the industry is shifting from monolithic architectures to modular quantum systems. By interconnecting multiple quantum processing units (QPUs) through communication links, modular quantum systems can scale to much higher number of qubits. However, the delay of inter-QPU operations is an order of magnitude greater than that of intra-QPU operations. To minimize the final circuit latency, a well-considered initial assignment of logical qubits in the circuit to QPUs in the system and careful insertion of inter-QPU operations are required. In this paper, we propose a timing-aware end-to-end circuit compilation framework for modular quantum systems. In the placement stage, a dependency- and interaction-aware assignment strategy is developed to assign logical qubits that interact early and frequently to nearby QPUs. In the routing stage, we optimize the insertion of inter-QPU operations and multiple intra-QPU operations to enable the execution of the gates. The selection of both inter- and intra-QPU operations is based on their circuit latency overhead, which is estimated using the operation delay and the available idle time of operand qubits that can cover the delay, as well as their benefit to subsequent gates. Our experiments assumed a realistic modular quantum system consisting of three interconnected QPUs with a total of 1,386 physical qubits. We evaluated our framework using two benchmark sets consisting of reversible arithmetic circuits and algorithmic circuits, with up to 1,300 qubits and over 800,000 two-qubit gates. Experimental results demonstrate that our approach outperformed the state-of-the-art compilation approach for modular quantum systems with over 73.8% and 46.9% reduction in final circuit latency and number of inserted inter-QPU operations, respectively. In addition, this advantage is preserved on a larger modular quantum system with four QPUs arranged in a square topology.
Scalable quantum computing requires execution models that go beyond the capacity of a single quantum processing unit (QPU). Although current hardware platforms continue to increase in qubit count, large fault-tolerant applications require substantially more physical qubits, stronger connectivity, and lower effective error rates than a monolithic near-term device can provide. Multi-QPU and multi-core architectures therefore form an important route towards larger quantum systems. However, distributing a quantum computation introduces compiler and architecture constraints that do not arise in conventional classical distribution. A partitioned quantum circuit separates gates and qubits that may still be logically entangled or mutually dependent. The system must therefore provide quantum resources that support entanglement between the distributed circuit fragments, while each local subcircuit must remain executable on the hardware topology of its assigned QPU. In this thesis, graph states serve as the explicit interconnection resources for these nonlocal dependences: they encode the entanglement structure required to support teleportation-based operations across QPUs. This thesis studies scalable quantum execution as an architecture-driven compilation problem. It develops a staged framework in which distribution, graph-state-based interconnection, and interconnection robustness are treated as dependent compiler decisions. The framework addresses three connected questions: 1) how a large quantum circuit should be divided when the resulting subcircuits must match real QPU topologies; 2) how the graph states required to entangle and operate across the distributed circuit boundaries can be prepared efficiently on constrained hardware; and 3) how those graph-state resources can remain useful under the loss and fusion failures that arise during preparation and use. These questions define an execution path from a large logical circuit to distributed local workloads connected by explicit entanglement resources. The thesis makes three main technical contributions that instantiate this framework. 1) It introduces hardware-aware circuit cutting, which incorporates the relationship between subcircuit interaction graphs and target QPU topology into the partitioning objective. This stage produces distributed workloads and explicit cut boundaries where quantum entanglement must be supplied across QPUs. 2) It formulates graph-state preparation as the resource-generation stage for those boundaries and develops methods that reduce preparation depth and emitter usage by exploiting graph-state equivalence and divide-and-conquer construction. 3) It develops a robust graph-state interconnection scheme that uses tree-encoded fusion and spin-memory-assisted compilation to tolerate photon loss and probabilistic fusion failures, so that the graph state can serve as a reliable connection between distributed quantum program fragments.