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arXiv:2511.04300

Self-correcting High-speed Opto-electronic Probabilistic Computer

Ramy Aboushelbaya, Annika Moslein, Hadi Azar, Hamid Tanhaei, Marko von der Leyen

quant-phcs.ETSubmitted Nov 6, 2025• Announced Nov 7, 2025• 0 citations
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Abstract

We present a novel self-correcting, high-speed optoelectronic probabilistic computer architecture that leverages source-device independent (SDI) quantum photonic p-bits integrated with robust electronic control. Our approach combines the intrinsic randomness and high bandwidth of quantum photonics with the programmability and scal- ability of classical electronics, enabling efficient and flexible probabilistic computation. We detail the design and implementation of a prototype system based on photonic integrated circuits and FPGA-based control, capable of implementing and manipulating 64000 logical p-bits. Experimental results demonstrate that our architecture achieves a flip rate of 2.7 x 10^9 flips/s with an energy consumption of 4.9 nJ/flip, representing nearly three orders of magnitude improvement in speed and energy efficiency compared to state-of-the-art magnetic tunnel junc- tion (MTJ) based systems. Furthermore, the SDI protocol enables real-time self-certification and error correction, ensuring reliable operation across a wide range of conditions and solving the problem of hardware variability as the number of p-bits scale. Our results establish quantum photonic p-bits as a promising platform for scalable, high-performance probabilistic computing, with significant implications for combinatorial optimization, machine learning, and complex system modeling.

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We present a novel self-correcting, high-speed optoelectronic probabilistic computer architecture that leverages source-device independent (SDI) quantum photonic p-bits integrated with robust electronic control. Our approach combines the intrinsic randomness and high bandwidth of quantum photonics with the programmability and scal- ability of classical electronics, enabling efficient and flexible probabilistic computation. We detail the design and implementation of a prototype system based on photonic integrated circuits and FPGA-based control, capable of implementing and manipulating 64000 logical p-bits. Experimental results demonstrate that our architecture achieves a flip rate of 2.7 x 10^9 flips/s with an energy consumption of 4.9 nJ/flip, representing nearly three orders of magnitude improvement in speed and energy efficiency compared to state-of-the-art magnetic tunnel junc- tion (MTJ) based systems. Furthermore, the SDI protocol enables real-time self-certification and error correction, ensuring reliable operation across a wide range of conditions and solving the problem of hardware variability as the number of p-bits scale. Our results establish quantum photonic p-bits as a promising platform for scalable, high-performance probabilistic computing, with significant implications for combinatorial optimization, machine learning, and complex system modeling.
Probabilistic machine learning utilizes controllable sources of randomness to encode uncertainty and enable statistical modeling. Harnessing the pure randomness of quantum vacuum noise, which stems from fluctuating electromagnetic fields, has shown promise for high speed and energy-efficient stochastic photonic elements. Nevertheless, photonic computing hardware which can control these stochastic elements to program probabilistic machine learning algorithms has been limited. Here, we implement a photonic probabilistic computer consisting of a controllable stochastic photonic element - a photonic probabilistic neuron (PPN). Our PPN is implemented in a bistable optical parametric oscillator (OPO) with vacuum-level injected bias fields. We then program a measurement-and-feedback loop for time-multiplexed PPNs with electronic processors (FPGA or GPU) to solve certain probabilistic machine learning tasks. We showcase probabilistic inference and image generation of MNIST-handwritten digits, which are representative examples of discriminative and generative models. In both implementations, quantum vacuum noise is used as a random seed to encode classification uncertainty or probabilistic generation of samples. In addition, we propose a path towards an all-optical probabilistic computing platform, with an estimated sampling rate of ~1 Gbps and energy consumption of ~5 fJ/MAC. Our work paves the way for scalable, ultrafast, and energy-efficient probabilistic machine learning hardware.
Probabilistic machine learning utilizes controllable sources of randomness to encode uncertainty and enable statistical modeling. Harnessing the pure randomness of quantum vacuum noise, which stems from fluctuating electromagnetic fields, has shown promise for high speed and energy-efficient stochastic photonic elements. Nevertheless, photonic computing hardware which can control these stochastic elements to program probabilistic machine learning algorithms has been limited. Here, we implement a photonic probabilistic computer consisting of a controllable stochastic photonic element - a photonic probabilistic neuron (PPN). Our PPN is implemented in a bistable optical parametric oscillator (OPO) with vacuum-level injected bias fields. We then program a measurement-and-feedback loop for time-multiplexed PPNs with electronic processors (FPGA or GPU) to solve certain probabilistic machine learning tasks. We showcase probabilistic inference and image generation of MNIST-handwritten digits, which are representative examples of discriminative and generative models. In both implementations, quantum vacuum noise is used as a random seed to encode classification uncertainty or probabilistic generation of samples. In addition, we propose a path towards an all-optical probabilistic computing platform, with an estimated sampling rate of ~ 1 Gbps and energy consumption of ~ 5 fJ/MAC. Our work paves the way for scalable, ultrafast, and energy-efficient probabilistic machine learning hardware.
The rapid rise of quantum computing and quantum internet highlights the irreplaceable importance of high-speed, scalable quantum randomness certification (QRC). However, existing QRC implementations are constrained by quantum measurement limits and integration bottlenecks, leaving both high-speed operation and monolithic implementation unrealized. Here, we demonstrate a monolithically integrated photonic–electronic on-chip source device-independent (SDI) quantum random number generator (QRNG) that achieves a secure bit rate of 583.2 Gbps within a compact 3 mm ×11 mm ×11 mm footprint, marking an advance in both integration and speed, nearly 30 times faster than the best existing integrated SDI implementations. By harnessing measurement-induced quantum uncertainty as a resource for quantum certification, this study resolves the challenge of uniting high-speed certified entropy bounds with full monolithic integration in SDI QRC. A universal entropy bound incorporating high-bandwidth physical constraints enables accurate entropy estimation under integrated conditions. This theoretical framework supports a four-path multi-interference measurement scheme that improves entropy yield and fills a critical gap in digital-layer security under coherent attacks. These contributions are experimentally embodied in a compact photonic–electronic chip that performs NIST-compliant secure entropy extraction, demonstrating the feasibility of combining high-speed performance with full system integration. Compatible with standard optical communication infrastructure, this study sets a new benchmark for scalable high-speed QRC, enabling robust security and broad applicability across quantum computing, the internet, and cryptography.
The slowing down of Moore’s Law has created an exciting new era of electronics, leading to the emergence of various types of CMOS+X devices and architectures. Here, we present the first experimental demonstration of a probabilistic computer where a stochastic magnetic tunnel junction (sMTJ) drives a powerful CMOS-based field programmable gate array (FPGA) in a heterogeneous compute fabric. We use our machine to experimentally evaluate the simulated quantum annealing (SQA) algorithm, known to closely mimic the behavior of D-Wave’s quantum annealers which implement the transverse field Ising model (TFIM). Our machine matches the exact solution of the TFIM where p-bits in the FPGA are asynchronously driven by the stochastic dynamics of a magnetic tunnel junction. To compare the performance of SQA against classical annealing (CA) in hard combinatorial optimization at large scale, we also design a fully digital emulator of our asynchronous architecture in the FPGA. Our digital system uses 7,085 p-bits to factor up to 26-bit integers and is about 10X faster than optimized Tensor (TPU) and Graphics Processing Units (GPU) at lower power. Surprisingly, we find that the additional replica networks necessary for SQA do not lead to appreciably better performance over an optimized CA that is using the same computational resources. The systematic evaluation of the SQA algorithm we present will be relevant for other types of accelerators, such as photonic or electronic Ising machines and the integrated scaling of our CMOS + sMTJ architecture could lead to orders of magnitude further improvements over TPU and GPUs, according to experimentally-validated projections.
The Ising annealing processor has emerged as a promising approach to accelerate the discovery of the optimal solutions for a wide range of combinatorial optimization problems (COPs), by mapping various COPs into a unified Ising model. However, fixed computational strategies and inflexible architectures make previous designs suffer from a low hardware resource utilization rate when the numbers of the total required and real-time flipped spins vary across different COPs and iteration steps. In this paper, a novel spin scale-aware self-adaptive Ising annealing processing architecture (AIAPA) is proposed to address this problem, with an adaptive computational strategy, a custom instruction set, multi-traffic mode routers, and a fully-pipelined computing array. It can dynamically adapt to the varying scenarios during the Ising annealing process to maximize the performance of limited hardware resources. Its prototype, supporting 65k fully-connected spins, is implemented on an FPGA platform, operates at a clock frequency of 188 MHz. The AIAPA achieves up to a 24.22 times faster annealing speed compared to the state-of-the-art FPGA design on the max-cut optimization problem while maintaining a high convergence accuracy.