Quantum kernels hold significant promise for achieving computational advantages in quantum machine learning (QML), yet their effectiveness critically depends on the design of expressive and hardware-compatible feature maps, a challenge that is particularly pronounced in Noisy Intermediate-Scale Quantum (NISQ) devices with limited qubits, gate errors, and restricted connectivity. In this work, we propose a hardware-aware methodology for automated quantum kernel design that integrates quantum device characteristics with learning-based evaluation. Specifically, candidate quantum circuits explored within the hardware-aware circuit space are represented as directed acyclic graphs (DAGs) encoding hardware-specific information such as gate operations, qubit interactions, and noise properties, while a dual graph neural network (GNN) predictor is employed to estimate key surrogate metrics, including probability of successful trials (PST) and kernel-target alignment (KTA), enabling efficient and accurate assessment of circuit fidelity and kernel performance to facilitate the identification of task-specific quantum kernels. Furthermore, feature selection is incorporated to reduce input dimensionality and ensure compatibility with near-term devices. Extensive experiments on multiple benchmark datasets, including Credit Card (CC), MNIST-5, and FMNIST-4, demonstrate that our method consistently outperforms existing baselines in classification accuracy, effectively balancing hardware constraints and model expressivity under realistic noise conditions. These results highlight the potential of combining hardware-aware design with deep learning techniques to advance practical quantum kernel methods under hardware-calibrated noisy simulation settings.
Quantum kernels hold significant promise for achieving computational advantages in quantum machine learning (QML), yet their effectiveness critically depends on the design of expressive and hardware-compatible feature maps, a challenge that is particularly pronounced in Noisy Intermediate-Scale Quantum (NISQ) devices with limited qubits, gate errors, and restricted connectivity. In this work, we propose a hardware-aware methodology for automated quantum kernel design that integrates quantum device characteristics with learning-based evaluation. Specifically, candidate quantum circuits explored within the hardware-aware circuit space are represented as directed acyclic graphs (DAGs) encoding hardware-specific information such as gate operations, qubit interactions, and noise properties, while a dual graph neural network (GNN) predictor is employed to estimate key surrogate metrics, including probability of successful trials (PST) and kernel-target alignment (KTA), enabling efficient and accurate assessment of circuit fidelity and kernel performance to facilitate the identification of task-specific quantum kernels. Furthermore, feature selection is incorporated to reduce input dimensionality and ensure compatibility with near-term devices. Extensive experiments on multiple benchmark datasets, including Credit Card (CC), MNIST-5, and FMNIST-4, demonstrate that our method consistently outperforms existing baselines in classification accuracy, effectively balancing hardware constraints and model expressivity under realistic noise conditions. These results highlight the potential of combining hardware-aware design with deep learning techniques to advance practical quantum kernel methods under hardware-calibrated noisy simulation settings.
The growing variety of quantum hardware technologies, each with unique peculiarities such as connectivity and native gate sets, creates challenges when selecting the best platform for executing a specific quantum circuit. This selection process usually involves a brute-force approach: compiling the circuit on various devices and evaluating performance based on factors such as circuit depth and gate fidelity. However, this method is computationally expensive and does not scale well as the number of available quantum processors increases. In this work, we propose a Graph Neural Network (GNN)based predictor that automates hardware selection by analyzing the Directed Acyclic Graph (DAG) representation of a quantum circuit. Our study evaluates 498 quantum circuits (up to 27 qubits) from the MQT Bench dataset, compiled using Qiskit on four devices: three superconducting quantum processors (IBM-Kyiv, IBM-Brisbane, IBM-Sherbrooke) and one trappedion processor (IONQ-Forte). Performance is estimated using a metric that integrates circuit depth and gate fidelity, resulting in a dataset where 93 circuits are optimally compiled on the trappedion device, while the remaining circuits prefer superconducting platforms. By exploiting graph-based machine learning, our approach avoids extracting the circuit features for the model evaluation but directly embeds it as a graph, significantly accelerating the optimal target decision-making process and maintaining all the information. Experimental results prove94.4%accuracy and an85.5%F1 score for the minority class, effectively predicting the best compilation target. The developed code is publicly available on GitHub (https://github.com/antotu/GNN-Model-Quantum-Predictor).
Quantum kernels hold great promise for offering computational advantages over classical learners, with the effectiveness of these kernels closely tied to the design of the quantum feature map. However, the challenge of designing effective quantum feature maps for real-world datasets, particularly in the absence of sufficient prior information, remains a significant obstacle. In this study, we present a data-driven approach that automates the design of problem-specific quantum feature maps. Our approach leverages feature-selection techniques to handle high-dimensional data on near-term quantum machines with limited qubits, and incorporates a deep neural predictor to efficiently evaluate the performance of various candidate quantum kernels. Through extensive numerical simulations on different datasets, we demonstrate the superiority of our proposal over prior methods, especially for the capability of eliminating the kernel concentration issue and identifying the feature map with prediction advantages. Our work not only unlocks the potential of quantum kernels for enhancing real-world tasks but also highlights the substantial role of deep learning in advancing quantum machine learning.
Deploying quantum machine learning algorithms on near-term quantum hardware requires circuits that respect device-specific gate sets, connectivity constraints, and noise characteristics. We present a hardware-aware Neural Architecture Search (NAS) approach for designing quantum feature maps that are natively executable on IBM quantum processors without transpilation overhead. Using genetic algorithms to evolve circuit architectures constrained to IBM Torino native gates (ECR, RZ, SX, X), we demonstrate that automated architecture search can discover quantum Support Vector Machine (QSVM) feature maps achieving competitive performance while guaranteeing hardware compatibility. Evaluated on the UCI Breast Cancer Wisconsin dataset, our hardware-aware NAS discovers a 12-gate circuit using exclusively IBM native gates (6 ECR, 3 SX, 3 RZ) that achieves 91.23 % accuracy on 10 qubits-matching unconstrained gate search while requiring zero transpilation. This represents a 27 percentage point improvement over hand-crafted quantum feature maps (64 % accuracy) and approaches the classical RBF SVM baseline (93 %). We show that removing architectural constraints (fixed RZ placement) within hardware-aware search yields 3.5 percentage point gains, and that 100 % native gate usage eliminates decomposition errors that plague universal gate compilations. Our work demonstrates that hardware-aware NAS makes quantum kernel methods practically deployable on current noisy intermediate-scale quantum (NISQ) devices, with circuit architectures ready for immediate execution without modification.
Abstract Noisy Intermediate-Scale Quantum (NISQ) computing is fundamentally constrained by hardware noise that is not only large but also temporally drifting and structurally complex. Traditional quantum error mitigation (QEM) techniques, such as Zero-Noise Extrapolation (ZNE), often rely on simplified noise assumptions that degrade under coherent errors and deep circuit structures. Conversely, existing machine learning-based QEM approaches typically treat device noise as a static background, leading to poor generalization when hardware calibration shifts. In this work, we propose \textbf{Calib-GNN}, a novel framework that explicitly integrates real-time hardware calibration data into a Graph Neural Network (GNN) architecture. By embedding gate-specific error rates directly into the graph representation, our model learns a dynamic mapping from noisy measurements to ideal expectation values. Through extensive simulations based on real noise profiles from the IBM Quantum \texttt{ibm\_fez} backend, we demonstrate that Calib-GNN significantly outperforms standard baselines. Specifically, it reduces the Root Mean Square Error (RMSE) by approximately 14\% compared to ZNE on random circuits and exhibits superior robustness against severe noise drift where traditional models fail. Furthermore, we show that Calib-GNN effectively scales to deeper circuits and recovers the ground state energy of the H2 molecule in Variational Quantum Eigensolver (VQE) tasks with high fidelity, overcoming the limitations of ZNE in the presence of coherent noise.
Quantum machine learning methods, including quantum kernels and variational quantum algorithms (VQAs), are poised to demonstrate quantum advantages in machine learning, chemistry, condensed matter physics, and materials science. However, these methods face critical challenges hindering practical quantum advantates: quantum kernels require meticulous design to outperform classical alternatives, while VQA training is obstructed by barren plateaus (BPs) in the optimization landscape. To address these issues, this thesis proposes two novel frameworks to guide quantum kernel design and tackle quantum neural network (QNN) training challenges in VQAs. Specifically, to resolve quantum kernel design challenges, we propose a data-driven method for automatic quantum kernel design, leveraging classical machine learning to learn from input data and identify optimal kernel structures. Experiments show this method finds suitable quantum kernels that avoid vanishing similarity, a common flaw in traditional designs. To improve VQA trainability, we propose an encoder-decoder parameter prediction framework, where a graph neural network (GNN) acts as the encoder to process information based on the QNN’s directed acyclic graph (DAG). Experiments confirm the parameters from this framework significantly enhance VQAs’ robustness, convergence speed, and trainability. In conclusion, we propose two schemes, QuKerNet and QuGHN, for automatic quantum kernel design and enhanced VQA trainability. QuKerNet considers optimal circuit layouts and variational parameters, and is more resource-efficient for contemporary quantum hardware by accounting for qubit topology and count. QuGHN is versatile, applicable to circuits with varying qubits, ansatzes, and tasks; its parameters enable faster convergence and more stable VQA solutions. These advancements enhance quantum machine learning practicality on near-term machines and its utility in large-scale quantum circuit simulations.
Designing parameterized quantum circuits (PQCs) that are expressive, trainable, and robust to hardware noise is a central challenge for quantum machine learning (QML) on noisy intermediate-scale quantum (NISQ) devices. We present a Domain-Aware Quantum Circuit (DAQC) that leverages image priors to guide locality-preserving encoding and entanglement via non-overlapping DCT-style zigzag windows. The design employs interleaved encode-entangle-train cycles, where entanglement is applied among qubits hosting neighboring pixels, aligned to device connectivity. This staged, locality-preserving information flow expands the effective receptive field without deep global mixing, enabling efficient use of limited depth and qubits. The design concentrates representational capacity on short-range correlations, reduces long-range two-qubit operations, and encourages stable optimization, thereby mitigating depth-induced and globally entangled barren-plateau effects. We evaluate DAQC on MNIST, FashionMNIST, and PneumoniaMNIST datasets. On quantum hardware, DAQC achieves performance competitive with strong classical baselines (e.g., ResNet-18/50, DenseNet-121, EfficientNet-B0) and substantially outperforming Quantum Circuit Search (QCS) baselines. To the best of our knowledge, DAQC, which uses a quantum feature extractor with only a linear classical readout (no deep classical backbone), currently achieves the best reported performance on real quantum hardware for QML-based image classification tasks. Code and pretrained models are available at: https://github.com/gurinder-hub/DAQC.