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arXiv:2506.15888 · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

Bias Variation Compensation in Perimeter-Gated SPAD TRNGs

Md Sajal, Hunter Guthrie, Marc P. Dandin

Published Aug 10, 2025• 0 citations
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Abstract

Random number generators that utilize arrays of entropy source elements suffer from bias variation (BV). Despite the availability of efficient debiasing algorithms, optimized implementations of hardware friendly options depend on the bit bias in the raw bit streams and cannot accommodate a wide BV. In this work, we present a$64 \times 64$array of perimeter gated single photon avalanche diodes (pgSPADs), fabricated in a$0.35 \mu ~\mathrm{m}$standard CMOS technology, as a source of entropy to generate random binary strings with a BV compensation technique. By applying proper gate voltages based on the devices' native dark count rates, we demonstrate less than 1 % BV for a raw-bit generation rate of$2 \text{kHz} /$pixel at room temperature. The raw bits were debiased using the classical iterative Von Neumann's algorithm and the debiased bits were found to pass all of the 16 tests from NIST's Statistical Test Suite.

DOI
10.1109/mwscas53549.2025.11244454

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Random number generators that utilize arrays of entropy source elements suffer from bias variation (BV). Despite the availability of efficient debiasing algorithms, optimized implementations of hardware friendly options depend on the bit bias in the raw bit streams and cannot accommodate a wide BV. In this work, we present a64×6464 \times 6464×64array of perimeter gated single photon avalanche diodes (pgSPADs), fabricated in a0.35μ m0.35 \mu ~\mathrm{m}0.35μ mstandard CMOS technology, as a source of entropy to generate random binary strings with a BV compensation technique. By applying proper gate voltages based on the devices' native dark count rates, we demonstrate less than 1 % BV for a raw-bit generation rate of2kHz/2 \text{kHz} /2kHz/pixel at room temperature. The raw bits were debiased using the classical iterative Von Neumann's algorithm and the debiased bits were found to pass all of the 16 tests from NIST's Statistical Test Suite.
This brief presents the application of perimeter-gated single-photon avalanche diodes (pg-SPADs) as true random number generators (TRNGs). Typical SPADs have been used as random number generators (RNGs) in photon-based or dark event-based configurations, and they utilize complex debiasing algorithms to increase their random bit efficiency (RBE). In contrast, we propose leveraging the dark count rate modulation property of pg-SPADs to enable true random number generation using simpler debiasing algorithms. Further, we demonstrate that perimeter gating may be used to maintain a constant dark count rate across a wide temperature range, conferring stability to the RNG in that range. A set of debiased random bits from a tested prototype chip was benchmarked against the National Institute of Standards and Technology (NIST) Statistical Test Suite (STS) with a success rate of 99.375%.
Combinatorial optimization problems are central to science and engineering and specialized hardware from quantum annealers to classical Ising machines are being actively developed to address them. These systems typically sample from a fixed energy landscape defined by the problem Hamiltonian encoding the discrete optimization problem. The recently introduced Probabilistic Approximate Optimization Algorithm (PAOA) takes a different approach: it treats the optimization landscape itself as variational, iteratively learning circuit parameters from samples. Here, we demonstrate PAOA on a 64$\times$64 perimeter-gated single-photon avalanche diode (pgSPAD) array fabricated in 0.35 μμμm CMOS, the first realization of the algorithm using intrinsically stochastic nanodevices. Each p-bit exhibits a device-specific, asymmetric (Gompertz-type) activation function due to dark-count variability. Rather than calibrating devices to enforce a uniform symmetric (logistic/tanh) activation, PAOA learns around device variations, absorbing residual activation and other mismatches into the variational parameters. On canonical 26-spin Sherrington-Kirkpatrick instances, PAOA achieves high approximation ratios with 2p2p2p parameters (ppp up to 17 layers), and pgSPAD-based inference closely tracks CPU simulations. These results show that variational learning can accommodate the non-idealities inherent to nanoscale devices, suggesting a practical path toward larger-scale, CMOS-compatible probabilistic computers.
The objective of this study is to generate random numbers using Single Photon Avalanche Diode (SPAD) native noise, specifically the Dark Count Rate (DCR). This is achieved by counting events over a fixed acquisition time window and creating a sequence of random bits using the least significant bits of the counter. A simple model was developed to evaluate the concept, which was then implemented on noisy SPADs integrated in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology, resulting in a compact 3D cell. The study tested the randomness quality of the measured bit sequences under various operating conditions, including voltage and temperature. The results indicate that the measured bit sequences pass successfully the NIST randomness quality tests under specific operating conditions. It is recommended to use the least significant bit and work with a sufficiently high excess voltage.
Single-Photon Avalanche Diodes (SPADs) are solid-state photo-detectors capable of detecting single photons by exploiting the avalanche effect that occurs in the breakdown of a p-n junction biased above breakdown voltage. By this effect, a SPAD translates an incoming photon to a macroscopic current pulse. These devices are currently used for building medical devices characterized by a very high time resolution. An appealing application of SPAD is to use them as a basic block for building the entropy source of true random number generators. In this paper we focus on such application, and we explore the design challenges behind the realization of a quantum random number generator based on a massively parallel array of SPADs. The matrix under investigation comprises 512×128 independent cells that convert photons onto a raw bit-stream, which, as ensured by the properties of quantum physics, is characterized by a very high level of randomness. The sequences are read out in a 128-bit parallel bus, concatenated, and pipelined onto a de-biasing filter. Subsequently, we fabricated the proposed chip using a standard CMOS process. Our results, achieved on the manufactured device and coupling two matrices, show that our architecture can reach up to 5 Gbit/s while consuming 25pJ/bit, thus demonstrating scalability and performance for any random number generators based on SPADs.
A random number generation approach comprising a silicon nanocrystals LED (Si-NCs LED), silicon single photon avalanche photodiode (Si SPAD) and a field-programmable gate array (FPGA) is introduced. The Si-NCs LED is the source of entropy with photon emission in the visible range detectable by silicon detectors allowing the fabrication of an all-silicon-based device. The proposed quantum random number generator (QRNG) is robust against variations of the internal and external parameters such as aging of the components, changing temperature, the ambient interferences and the silicon detector artifacts. The raw data show high quality of randomness and passed all the statistical tests in National Institute of Standards and Technology (NIST) tests suite without the application of a post-processing algorithm. The efficiency of random number generation is 4-bits per detected photon.
Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs, there is often little modeling or analytical description of the entropy source, circuit extraction, and post-processing provided. In this work, we present a single-photon avalanche diode (SPAD)-based QRNG design, which utilizes the quantum random flip-flop (QRFF) method. Extensive modeling of detector and circuit imperfections that result in entropy degradation is performed. A new method to analytically model serial autocorrelations of the proposed bit generation method, which includes detector dead time, is proposed. Then, a Verilog-AMS model is developed in order to validate the analytical model in simulation. A novel transistor implementation of the QRFF circuit is presented, which enables compensation of the degradation in entropy inherent to the finite non-symmetric transitions of the random flip-flop. Finally, a full system containing two independent arrays of the QRFF circuit is manufactured and tested in a 55-nm bipolar–CMOS–DMOS (BCD) technology node, demonstrating bit generation statistics that are commensurate to the developed model. The full chip is able to generate 3.3 Gb/s of data when operated with an external LED. Pixelwise and spatial analysis of bias and correlation is performed. NIST STS (SP 800-22) and SP 800-90B are used to benchmark the generated bit strings.