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arXiv:2506.08182 · Quantum

Quantum Resource Comparison for Two Leading Surface Code Lattice Surgery Approaches

Tyler LeBlond, Ryan S. Bennink

Published Aug 10, 2026• 0 citations
arXivHTMLPDF

Abstract

Hamiltonian simulation is one of the most promising candidates for the demonstration of quantum advantage within the next ten years, and several studies have proposed end-to-end resource estimates for executing such algorithms on fault-tolerant quantum processors. Usually, these resource estimates are based upon the assumption that quantum error correction is implemented using the surface code, and that the best surface code compilation scheme involves serializing input circuits by eliminating all Clifford gates. This transformation is thought to make best use of the native multi-body measurement (lattice surgery) instruction set available to surface codes. Some work, however, has suggested that direct compilation from Clifford+T to lattice surgery operations may be beneficial for circuits that have high degrees of logical parallelism. In this study, we analyze the resource costs for implementing Hamiltonian simulation using example approaches from each of these leading surface code compilation families. The Hamiltonians whose dynamics we consider are those of the transverse-field Ising model in several geometries, the Kitaev honeycomb model, and the α − R u C l 3 complex under a time-varying magnetic field. We show, among other things, that the optimal scheme depends on whether Hamiltonian simulation is implemented using the quantum signal processing or Trotter-Suzuki algorithms, with Trotterization benefiting by orders of magnitude from direct Clifford+T compilation for these applications. Our results suggest that surface code quantum computers should not have a one-size-fits-all compilation scheme, but that smart compilers should predict the optimal scheme based upon high-level quantities from logical circuits such as average circuit density, numbers of logical qubits, and T fraction.

DOI
10.22331/q-2026-08-10-2187

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Hamiltonian simulation is one of the most promising candidates for the demonstration of quantum advantage within the next ten years, and several studies have proposed end-to-end resource estimates for executing such algorithms on fault-tolerant quantum processors. Usually, these resource estimates are based upon the assumption that quantum error correction is implemented using the surface code, and that the best surface code compilation scheme involves serializing input circuits by eliminating all Clifford gates. This transformation is thought to make best use of the native multi-body measurement (lattice surgery) instruction set available to surface codes. Some work, however, has suggested that direct compilation from Clifford+T to lattice surgery operations may be beneficial for circuits that have high degrees of logical parallelism. In this study, we analyze the resource costs for implementing Hamiltonian simulation using example approaches from each of these leading surface code compilation families. The Hamiltonians whose dynamics we consider are those of the transverse-field Ising model in several geometries, the Kitaev honeycomb model, and the α − R u C l 3 complex under a time-varying magnetic field. We show, among other things, that the optimal scheme depends on whether Hamiltonian simulation is implemented using the quantum signal processing or Trotter-Suzuki algorithms, with Trotterization benefiting by orders of magnitude from direct Clifford+T compilation for these applications. Our results suggest that surface code quantum computers should not have a one-size-fits-all compilation scheme, but that smart compilers should predict the optimal scheme based upon high-level quantities from logical circuits such as average circuit density, numbers of logical qubits, and T fraction.
In the early fault-tolerant quantum computing era, it is desirable to accurately capture resource estimates for practical quantum circuit execution on future fault-tolerant quantum processors. While several open-source resource estimation tools currently exist, they fall short of realism in multiple facets: first, they do not rely on explicit compilation, thus necessitating several simplifying assumptions. Second, they rely on one-size-fits-all logical error rate formulae for all members of their logical instruction set. To properly account for the resource overhead of fault-tolerance, a comprehensive strategy for compiling logical circuits into fault-tolerant operations on a hardware-mapped quantum error-correcting code is required. In the case of the surface code, explicit compilation enables resource estimation for schemes that do not assume a constant rate of magic state consumption and the more realistic computation of total logical error based on active hardware tiles. This poster will focus on ORNL's efforts toward developing compiler-based resource estimation for a surface code mapping onto a hypothetical trappedion QCCD architecture. To this end, two open-source compilers and a simulator have been developed. First, we use a significantly-revised Lattice Surgery Compiler (LSC) to compile logical circuits into surface code primitives acting on abstract hardware tiles. Second, the Trapped-Ion Surface Code Compiler (TISCC) compiles these primitives into native trappedion hardware gates acting on trapping zones. Finally, we use the Oak Ridge Quasi-Clifford Simulator (ORQCS) to evaluate the fault-tolerance of TISCC circuits under realistic trappedion QCCD noise assumptions. We describe how this end-to-end fault-tolerance compilation and simulation capability enables advanced resource estimation.
We report a resource estimation pipeline that explicitly compiles quantum circuits expressed using the Clifford+T gate set into a surface code lattice surgery instruction set. The cadence of magic state requests from the compiled circuit enables the optimization of magic state distillation and storage requirements in a post-hoc analysis. To compile logical circuits into lattice surgery operations, we build upon the open-source Lattice Surgery Compiler. The revised compiler operates in two stages: the first translates logical gates into an abstract, layout-independent instruction set; the second compiles these into local lattice surgery instructions that are allocated to hardware tiles according to a specified resource layout. The second stage retains logical parallelism while avoiding resource contention in the fault-tolerant layer, aiding realism. Additionally, users can specify dedicated tiles at which magic states are replenished, enabling resource costs from the logical computation to be considered independently from magic state distillation and storage. We demonstrate the applicability of our pipeline to large practical quantum circuits by providing resource estimates for the ground state estimation of molecules. We find that variable magic state consumption rates in real circuits can cause the resource costs of magic state storage to dominate unless production is varied to suit.
Lattice surgery on the surface code is a leading route to fault-tolerant quantum computation. Compiling logical circuits into lattice surgery operations is a pivotal step that determines the resource cost of a computation. Prior compilers build on idealized assumptions, and one that works in practical settings remains to be developed. Existing works are either unscalable or route one gate at a time within a layer, so the embedding depends on the order of gates and opportunities to route many gates at once are lost. In addition, they assume magic states are always available and cost-free, even though preparing one costs more than a Clifford operation. We present FlowRouter, the first topological lattice surgery compiler that places Clifford routing and stochastic magic state cultivation inside a single 3D embedding. At compile time, FlowRouter formulates the routing of an entire circuit layer as a maximum-flow problem, embedding many gates simultaneously. At runtime, it allows magic states to be cultivated at every idling patch, works with the realistic cultivation process with multiplexing and multi-stage post-selections, and absorbs the stochasticity by introducing delay mechanisms that add as little spacetime volume as possible. With magic states assumed free, FlowRouter reduces spacetime volume by 2.3x and compiles 10.8x faster than the state-of-the-art static topological lattice surgery compiler. With the cultivation-aware setting that includes both Clifford and magic state cost, FlowRouter reduces spacetime volume by 2.3x on a distance-13 surface code when compared with the state-of-the-art runtime compiler.
Recent experimental progress in realizing surface code on hardware, including demonstrations of break-even logical memory on devices with up to hundreds of physical qubits, has materially advanced the prospects for fault-tolerant quantum computation. This progress creates urgency for the development of compilation workflows that directly target the forthcoming generation of devices with thousands of physical qubits, for which algorithm execution becomes practical. We develop a pipeline for compiling logical algorithms to physical circuits implementing lattice surgery on the surface code, and use this pipeline to identify the requirements for achieving algorithmic break-even -- where quantum error correction improves the performance of a quantum algorithm -- for two prominent quantum algorithms: the quantum approximate optimization algorithm (QAOA) and quantum phase estimation (QPE). Our pipeline integrates several open-source software tools, and leverages recent advances in error-aware unitary gate synthesis, high-fidelity magic state production, and the calculation of correlation surfaces in the surface code. We perform classical simulations of physical Clifford proxy circuits produced by our pipeline, and find that both 5-qubit QAOA and QPE can reach algorithmic break-even with 2517 physical qubits (surface code distance d=11d=11d=11) at physical error rates of p=10−3p=10^{-3}p=10−3, or 1737 physical qubits (d=9d=9d=9) at p=5×10−4p=5\times 10^{-4}p=5×10−4. Our work thereby identifies conditions for achieving algorithmic break-even with near-term quantum hardware and paves the way towards an end-to-end compiler for early-fault-tolerant surface code architectures.
The emerging field of quantum resource estimation is aimed at providing estimates of the hardware requirements (`quantum resources') needed to execute a useful, fault-tolerant quantum computation. Given that quantum computers are intended to compete with supercomputers, useful quantum computations are likely to involve the use of millions of qubits and error correction clock cycles. The compilation and benchmarking of these circuits depends on placement and routing algorithms, which are infeasible to construct at scale by hand. We offer a compiler that transforms a quantum circuit into a sequence of lattice surgery operations. The compiler manages memory in terms of surface code patches and costs the space-time volume and cycle counts of the input circuits. These compiled lattice surgery objects are then recursively repurposed as gates for larger scale compilations. Our code is available on GitHub under a permissive software license and we welcome community contributions.
We present the first high performance compiler for very large scale quantum error correction: it translates an arbitrary quantum circuit to surface code operations based on lattice surgery. Our compiler offers an end to end error correction workflow implemented by a pluggable architecture centered around an intermediate representation of lattice surgery instructions. Moreover, the compiler supports customizable circuit layouts, can be used for quantum benchmarking and includes a quantum resource estimator. The compiler can process millions of gates using a streaming pipeline at a speed geared towards real-time operation of a physical device. We compiled within seconds 80 million logical surface code instructions, corresponding to a high precision Clifford+T implementation of the 128-qubit Quantum Fourier Transform (QFT).