Fast execution of complex quantum circuit simulations are crucial for verification of theoretical algorithms paving the way for their successful execution on the quantum hardware. However, the main stream CPU-based platforms for circuit simulation are well-established but slower. Despite this, adoption of GPU platforms remains limited because different hardware architectures require specialized quantum simulation frameworks, each with distinct implementations and optimization strategies. Therefore, we introduce Q-Gear, a software framework that transforms Qiskit quantum circuits into Cuda-Q kernels. By leveraging Cuda-Q seamless execution on GPUs, Q-Gear accelerates both CPU and GPU based simulations by respectively two orders of magnitude and ten times with minimal coding effort. Furthermore, Q-Gear leverages Cuda-Q configuration to interconnect GPUs memory allowing the execution of much larger circuits, beyond the memory limit set by a single GPU or CPU node. Additionally, we created and deployed a Podman container and a Shifter image at Perlmutter (NERSC/LBNL), both derived from NVIDIA public image. These public NERSC containers were optimized for the Slurm job scheduler allowing for close to 100% GPU utilization. We present various benchmarks of the Q-Gear to prove the efficiency of our computation paradigm.
Fast execution of complex quantum circuit simulations are crucial for verification of theoretical algorithms paving the way for their successful execution on the quantum hardware. However, the main stream CPU-based platforms for circuit simulation are well-established but slower. Despite this, adoption of GPU platforms remains limited because different hardware architectures require specialized quantum simulation frameworks, each with distinct implementations and optimization strategies. Therefore, we introduce Q-Gear, a software framework that transforms Qiskit quantum circuits into Cuda-Q kernels. By leveraging Cuda-Q seamless execution on GPUs, Q-Gear accelerates both CPU and GPU based simulations by respectively two orders of magnitude and ten times with minimal coding effort. Furthermore, Q-Gear leverages Cuda-Q configuration to interconnect GPUs memory allowing the execution of much larger circuits, beyond the memory limit set by a single GPU or CPU node. Additionally, we created and deployed a Podman container and a Shifter image at Perlmutter (NERSC/LBNL), both derived from NVIDIA public image. These public NERSC containers were optimized for the Slurm job scheduler allowing for close to 100% GPU utilization. We present various benchmarks of the Q-Gear to prove the efficiency of our computation paradigm.
The rapid execution of complex quantum circuit simulations is essential for validating theoretical algorithms, thereby facilitating their successful implementation on quantum hardware. Although mainstream CPU-based platforms for circuit simulations are well established, they tend to be slower. Conversely, the adoption of GPU platforms remains limited because of the necessity for specialized quantum simulation frameworks tailored to different hardware architectures, each requiring distinct implementation and optimization strategies. Therefore, we introduced Q-Gear, a platform-agnostic framework that transforms Qiskit quantum circuits into Cuda-Q kernels. By leveraging Cuda-Q seamless execution on GPUs, Q-Gear accelerates both CPU- and GPU-based simulations by two orders of magnitude and ten times, respectively, with minimal coding effort. Furthermore, Q-Gear leverages the Cuda-Q configuration to interconnect the memory of GPUs, allowing the execution of much larger circuits beyond the memory limit set by a single GPU or CPU node. Additionally, we created and deployed a Podman container and Shifter image at Perlmutter (NERSC/LBNL), both derived from an NVIDIA public image. These public NERSC containers were optimized for the Slurm job scheduler, allowing approximately 100% utilization of up to 1,024 GPUs. We present various benchmarks for Q-Gear to demonstrate the efficiency of our computational paradigm.
The rapid execution of complex quantum circuit simulations is essential for validating theoretical algorithms, thereby facilitating their successful implementation on quantum hardware. Although mainstream CPU-based platforms for circuit simulations are well established, they tend to be slower. Conversely, the adoption of GPU platforms remains limited because of the necessity for specialized quantum simulation frameworks tailored to different hardware architectures, each requiring distinct implementation and optimization strategies. Therefore, we introduced Q-Gear, a platform-agnostic framework that transforms Qiskit quantum circuits into Cuda-Q kernels. By leveraging Cuda-Q seamless execution on GPUs, Q-Gear accelerates both CPU- and GPU-based simulations by two orders of magnitude and ten times, respectively, with minimal coding effort. Furthermore, Q-Gear leverages the Cuda-Q configuration to interconnect the memory of GPUs, allowing the execution of much larger circuits beyond the memory limit set by a single GPU or CPU node. Additionally, we created and deployed a Podman container and Shifter image at Perlmutter (NERSC/LBNL), both derived from an NVIDIA public image. These public NERSC containers were optimized for the Slurm job scheduler, allowing approximately 100% utilization of up to 1,024 GPUs. We present various benchmarks for Q-Gear to demonstrate the efficiency of our computational paradigm.
Classical simulation of quantum circuits remains indispensable for algorithm development, hardware validation, and error analysis in the noisy intermediate-scale quantum (NISQ) era. However, state-vector simulation faces exponential memory scaling, with an n-qubit system requiring O(2^n) complex amplitudes, and existing simulators often lack the flexibility to exploit heterogeneous computing resources at runtime. This paper presents a GPU-accelerated quantum circuit simulation framework that introduces three contributions: (1) an empirical backend selection algorithm that benchmarks CuPy, PyTorch-CUDA, and NumPy-CPU backends at runtime and selects the optimal execution path based on measured throughput; (2) a directed acyclic graph (DAG) based gate fusion engine that reduces circuit depth through automated identification of fusible gate sequences, coupled with adaptive precision switching between complex64 and complex128 representations; and (3) a memory-aware fallback mechanism that monitors GPU memory consumption and gracefully degrades to CPU execution when resources are exhausted. The framework integrates with Qiskit, Cirq, PennyLane, and Amazon Braket through a unified adapter layer. Benchmarks on an NVIDIA A100-SXM4 (40 GiB) GPU demonstrate speedups of 64x to 146x over NumPy CPU execution for state-vector simulation of circuits with 20 to 28 qubits, with speedups exceeding 5x from 16 qubits onward. Hardware validation on an IBM quantum processing unit (QPU) confirms Bell state fidelity of 0.939, a five-qubit Greenberger-Horne-Zeilinger (GHZ) state fidelity of 0.853, and circuit depth reduction from 42 to 14 gates through the fusion pipeline. The system is designed for portability across NVIDIA consumer and data-center GPUs, requiring no vendor-specific compilation steps.
The rapid expansion of quantum computing research has created a growing need for effective and scalable tools to simulate quantum algorithms. In this study, we present a performance analysis of several quantum circuit simulators by using the Deutsch-Jozsa (DJ) and Quantum Fourier Transform (QFT). A gate-based QASM implementation serves as the baseline and is converted to code compatible with each simulator. Our evaluation covers multi-CPU simulators like Qiskit, Qsim-Cirq, and QuEST, as well as their GPU-accelerated variants along with CUDA-Q, for qubit sizes ranging from 21 to 35. By profiling these algorithms, we compare key performance indicators and reveal notable efficiency differences between platforms. In particular, the multi-node version of QuEST shows strong CPU utilization, high speedup, and efficient memory scalability. whereas GPUbased implementations provide clear performance advantages at higher qubit counts. These findings offer practical guidance for choosing simulation platforms according to problem size and available computing resources, thereby supporting more efficient quantum-algorithm workflows.
The Quantum Approximate Optimization Algorithm (QAOA) is a prominent quantum algorithm designed to find approximate solutions to combinatorial optimization problems, which are challenging for classical computers. In the current era, where quantum hardware is constrained by noise and limited qubit availability, simulating the QAOA remains essential for research. However, existing state-of-the-art simulation frame-works suffer from long execution times or lack comprehensive functionality, usability, and versatility, often requiring users to implement essential features themselves. Additionally, these frameworks are primarily restricted to Python, limiting their use in safer and faster languages like Rust, which offer, e.g., advanced parallelization capabilities. In this paper, we develop a GPU accelerated QAOA simulation framework utilizing the NVIDIA CUDA toolkit. This framework offers a complete interface for QAOA simulations, enabling the calculation of (exact) expectation values, direct access to the statevector, fast sampling, and high-performance optimization methods using an advanced state-of-the-art gradient calculation technique. The framework is designed for use in Python and Rust, providing flexibility for integration into a wide range of applications, including those requiring fast algorithm implementations leveraging QAOA at its core. The new framework's performance is rigorously benchmarked on the MaxCut problem and compared against the current state-of-the-art general-purpose quantum circuit simulation frameworks Qiskit and Pennylane as well as the specialized QAOA simulation tool QOKit. Our evaluation shows that our approach outperforms the existing state-of-the-art solutions in terms of runtime up to multiple orders of magnitude. Our implementation is publicly available at https://github.com/JFLXB/cuaoa and Zenodo [1].
This work presents a portable, modular quantumcircuit emulator designed to accelerate algorithm prototyping by leveraging Central Processing Unit (CPU) and Compute Unified Device Architecture (CUDA)-enabled Graphic Processing Unit (GPU) backends for dense linearalgebra workloads.The emulator provides a lightweight backend abstraction that unifies NumPy and CuPy, supports both statevector and density-matrix representations, and implements efficient multi-target unitary embedding and Kraus-map noise channels.These capabilities enable rapid exploration of quantum algorithms that require full 2 n × 2 n operators, such as quantum phase estimation, full Quantum Fourier Transform (QFT), and noise-aware variational circuits, while minimizing host/device transfer and preserving numerical parity between backends.Implementation strategies are described for embedding single-and multi-qubit gates, parameterized rotations, and controlled unitaries, along with an "apply_unitary_on_targets" routine that employs reshape/matrix-multiply/reshape patterns to map arbitrary target sets to dense GPU kernels for high throughput.Using a curated benchmark suite of dense quantum workloads and microbenchmarks, including large matrix multiplies and Fast Fourier Transforms (FFT), performance is quantified across a range of qubit counts and precisions.The results demonstrate substantial speedups on modern NVIDIA GPUs for workloads dominated by dense linear algebra, identify cross-over points where GPU acceleration becomes beneficial, and analyse memory/precision trade-offs for complex64 versus complex128.The presented emulator lowers the barrier for noise-aware algorithm prototyping by combining practical software ergonomics with GPU performance, enabling faster iteration on algorithm design and noise-mitigation strategies on commodity single-node hardware.While the abstraction layer ensures portability, achieving peak performance currently requires hardwarespecific tuning-a limitation we address through future automation strategies.