arXiv:2501.12470 · ACM Transactions on Quantum Computing

Efficient Compilation for Shuttling Trapped-Ion Machines via the Position Graph Architectural Abstraction

Bao Gia Bach, Ilya Safro, Ed Younis

Published Jul 14, 2026• 0 citations

Abstract

With the growth of quantum platforms for gate-based quantum computation, compilation holds a crucial role in deciding the success of the implementation. While there has been rich research in compilation techniques for the superconducting-qubit regime. The trapped-ion architectures, currently leading in robust quantum computations for their reliable operations, still lack competitive compilation strategies. This work introduces a unifying hardware abstraction, the “position graph”, representing various hardware architectures. With this abstraction, we model trapped-ion Quantum Charge-Coupled Device (QCCD) architectures, enabling high-quality, scalable compilation methods. Specifically, we propose scheduling algorithms called SHuttling-Aware PERmutative (SHAPER) and SHuttling-AWare (SHAW) heuristic searches to tackle the complex constraints and dynamics of trapped-ion machines, with the cooperation of state-of-the-art permutation-aware mapping. These approaches generate executable circuits and native instructions that respect the physical constraints of shuttling-based architectures. We evaluate proposed algorithms across theorized and real architectures using the position graph framework. For completeness, we also introduce a linear program of trapped-ion scheduling that yields the optimal schedules, enabling a direct comparison with our heuristics. Our algorithm can successfully compile programs for extreme architectures where prior algorithms fail. When the baseline does complete, our produced schedules are 1.45 times faster on average, with best-case speedups up to 4 times faster.

DOI: 10.1145/3831246

Related papers

Scaling Qubit Mapping and Routing With Position Graph Abstraction and Memoization

Brent Russon, Bao Bach, Ed Younis +1 more

Scalable qubit mapping and routing remain major bottlenecks in quantum compilation, especially for Trapped-Ion Quantum Charge-Coupled device (TI-QCCD) architectures, where qubit interactions require physically shuttling ions under strict movement, congestion, and trap-capacity constraints. We present a compilation framework built around the position graph abstraction, a unified representation of executable locations, movement paths, and routing constraints that enables heuristic mappers to operate directly on shuttling-based hardware. Using this abstraction, we accelerate the SWAP-based BidiREctional heuristic search (SABRE) by implementing relative move scoring, which caches repeated heuristic move evaluations that arise during search, and memoized congestion resolution, which speeds up the resolution of repeated congestion. This optimization removes redundant computation without changing routing/shuttling decisions, improving the scalability of SABRE-based methods on TI-QCCD systems. Our results show that combining an architecture-aware abstraction with memoized heuristic evaluation yields a practical and effective path toward scalable qubit mapping and routing across heterogeneous quantum architectures.

quant-pharXiv:2605.09237May 12, 20260 citations

An Improved Ion-Shuttling Approach for QCCD Architectures

Tung-Yeh Wu, Ting-Chi Wang

Trapped-ion quantum computers offer high-fidelity operations, long coherence times, and all-to-all connectivity within a single trap. However, scaling to large circuits is limited by the trap's ion capacity. The QCCD architecture addresses this by enabling ion shuttling across multiple traps, but excessive shuttling increases execution time and degrades fidelity. This paper presents an improved ion-shuttling approach targeting linear QCCD architectures. Building on a state-of-the-art approach [27] for linear trapped-ion devices, our approach introduces a front-layer-based scheduling method that dynamically prioritizes executable gates, along with a novel destination trap selection method for ion-shuttling, effectively reducing unnecessary ion movements. We also present a look-ahead gate selection strategy based on the gate dependency graph, avoiding the high runtime of the gate proximity approach used in the state-of-the-art approach, especially in circuits with all-to-all communication. Our approach achieves up to a 37.67% reduction in shuttle count and up to a 74.91% reduction in compilation time compared to the state-of-the-art approach for linear trapped-ion devices on actual NISQ benchmarks and synthetic circuits. On average, our approach achieves a 16.44% reduction in shuttle count and a 30.77% reduction in compilation time across all test cases. These improvements highlight the effectiveness of our approach, particularly for actual circuits.

International Symposium on Physical DesignMar 15, 20260 citations

Orchestrating Multi-Zone Shuttling in Trapped-Ion Quantum Computers

Daniel Schoenberger, Robert Wille

Trapped-ion quantum computers are a promising platform, offering high-quality qubits with long coherence times and high-fidelity gate operations. The Quantum Charge Coupled Device (QCCD) architecture provides a scalable blueprint by leveraging the ability to shuttle ions between distinct zones. However, realizing such architectures in practice requires software support to manage ion movement across multi-zone layouts. In this work, we propose a compilation strategy for QCCD architectures with multiple processing zones located outside a grid-type memory zone. Unlike previous approaches that treat processing zones as black-boxes, our method explicitly models their structural constraints, enabling optimized ion movement to and through them. It combines qubit partitioning with dependency-aware gate selection to reduce inter-zone shuttling while enabling simultaneous gate execution. We implemented the method in an open-source tool and empirically demonstrated its effectiveness across several QCCD layouts, laying a foundation for the compilation of multi-zone trapped-ion systems.

IEEE International Conference on Quantum Computing and Engineering (QCE)Aug 30, 20251 citation

Shuttling for Scalable Trapped-Ion Quantum Computers

Daniel Schoenberger, Stefan Hillmich, Matthias Brandl +1 more

Trapped-ion quantum computers exhibit promising potential to provide platforms for high-quality qubits and reliable quantum computation. The quantum charge coupled device (QCCD) architecture is a leading example that offers a modular solution to enable the realization of scalable quantum computers, paving the way for practical quantum algorithms with large qubit numbers. Within these devices, ions can be shuttled (moved) throughout the trap and through different dedicated zones, e.g., a memory zone for storage and a processing zone for the actual computation. However, due to decoherence of the ions’ quantum states, the qubits lose their quantum information over time. Thus, the required time steps of shuttling operations should be minimized. In this work,1 we propose a heuristic approach to determining an efficient shuttling schedule, which orchestrates the movement operations within the device. Given a quantum algorithm and a device architecture, the proposed approach produces shuttling schedules with a close-to-minimal amount of time steps for small-size QCCD architectures. For large-scale QCCD devices, empirical evaluations show promising results with respect to quality of the solution as well as performance. An implementation of the proposed approach is publicly available as part of the open-source Munich Quantum Toolkit (MQT) athttps://github.com/cda-tum/mqt-ion-shuttler.

arXiv:2402.14065IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsDec 9, 202429 citations

From QCCD Trapped-Ion Hardware to Quantum Compilers: Capabilities, Architectures, and Compilation

Ludwig Schmid, Jurek Eisinger, Daniel Schoenberger +5 more

Shuttling-based trapped-ion quantum computers (QCCD) rank among the most mature hardware platforms. Existing and envisaged devices exhibit architectural differences in terms of register layout and connectivity. Platform-specific compilers are required to translate quantum circuits into resource-optimized hardware-level command chains. Hardware platforms and compiler software stacks are mostly developed independently of one another by different research communities. This work aims to bridge these communities by abstracting QCCD architectures and native operations, enabling computer scientists to address compilation problems using generic methods without requiring a deep background in the physical operating principles of the platform. The resulting design space is organized into a small set of architectural archetypes, each posing its own compilation problem. We then select and apply compilation methods to one- and two-dimensional QCCD architectures, finding that the routing overhead scales approximately cubically with the number of qubits for the one-dimensional architecture and approximately quadratically for the two-dimensional one. Extending this to compilation with a quantum error-correction layer reveals additional differences and similarities between the physical and logical levels. We conclude that co-design is a requirement rather than an option, and this work provides the vocabulary, archetypes, and compilation abstraction it needs.

quant-pharXiv:2610.36965Oct 28, 20260 citations

Shuttling Compiler for Trapped-Ion Quantum Computers Based on Fine-Tuned Large Language Models

Fabian Kreppel, Reza Salkhordeh, Ferdinand Schmidt-Kaler +1 more

In trapped-ion quantum computers, qubits must be shuttled between segments to interact. The routing logic that schedules these movements is written by hand for every new trap architecture. We present shuttling compilers based on five large language models (LLMs). Each LLM is fine-tuned on shuttling schedules produced by hand-coded heuristics for linear and branched one-dimensional trap architectures. We investigate how the shuttling operation counts of their schedules compare with those of the heuristics and how far they generalize to unseen architectures. For circuits of up to 16 qubits, the fine-tuned LLMs generate valid schedules on both training architectures, more often the fewer qubits a circuit has. In 12% of the compilations yielding a schedule, the best of ten runs needs up to 21% fewer operations than the heuristic baselines, after a rule-based post-processing step. A single run of one fine-tuned LLM produces a valid shuttling schedule for a previously unseen four-way branched architecture. This is preliminary evidence of cross-architecture generalization. On two other unseen architectures no LLM produces a valid schedule. Thus, LLM-learned shuttling compilation is feasible, and we show how far it currently reaches.

quant-pharXiv:2512.18021Dec 23, 20250 citations