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arXiv:2412.15751

Implementation of Magic State Injection within Heavy-Hexagon Architecture

Hansol Kim, Choi, Wonjae, Younghun Kwon

Published Dec 20, 2024• 0 citations
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Abstract

The magic state injection process is a critical component of fault-tolerant quantum computing, and numerous studies have been conducted on this topic. Many existing studies have focused on square-lattice structures, where each qubit connects directly to four other qubits via two-qubit gates. However, hardware that does not follow a lattice structure, such as IBM's heavy-hexagon structure, is also under development. In these non-lattice structures, many quantum error correction (QEC) codes designed for lattice-based system cannot be directly applied. Adapting these codes often requires incorporating additional qubits, such as flag qubits. This alters the properties of the QEC code and introduces new variables into the magic state injection process. In this study, we implemented and compared the magic state injection process on a heavy-hexagon structure with flag qubits and a lattice structure without flag qubits. Additionally, we considered biased errors in superconducting hardware and investigated the impact of flag qubits under these conditions. Our analysis reveals that the inclusion of flag qubits introduces distinct characteristics into the magic state injection process, which are absent in systems without flag qubits. Based on these findings, we identify several critical considerations for performing magic state injection on heavy-hexagon systems incorporating flag qubits. Furthermore, we propose an optimized approach to maximize the efficacy of this process in such systems.

DOI
10.48550/arxiv.2412.15751

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The magic state injection process is a critical component of fault-tolerant quantum computing, and numerous studies have been conducted on this topic. Many existing studies have focused on square-lattice structures, where each qubit connects directly to four other qubits via two-qubit gates. However, hardware that does not follow a lattice structure, such as IBM's heavy-hexagon structure, is also under development. In these non-lattice structures, many quantum error correction (QEC) codes designed for lattice-based system cannot be directly applied. Adapting these codes often requires incorporating additional qubits, such as flag qubits. This alters the properties of the QEC code and introduces new variables into the magic state injection process. In this study, we implemented and compared the magic state injection process on a heavy-hexagon structure with flag qubits and a lattice structure without flag qubits. Additionally, we considered biased errors in superconducting hardware and investigated the impact of flag qubits under these conditions. Our analysis reveals that the inclusion of flag qubits introduces distinct characteristics into the magic state injection process, which are absent in systems without flag qubits. Based on these findings, we identify several critical considerations for performing magic state injection on heavy-hexagon systems incorporating flag qubits. Furthermore, we propose an optimized approach to maximize the efficacy of this process in such systems.
Implementing fault-tolerant quantum computing necessitates the realization of logical non-Clifford gates, which requires the preparation of specific quantum states known as magic states. However, IBM’s heavy-hexagon structure, which has limited qubit connectivity, presents challenges in adapting quantum error correction codes such as the surface code. Several methods have been proposed to address these challenges by adapting the surface code to the heavy-hexagon architecture. In this study, we implement the magic state injection process within two distinct implementations of surface codes (standard and rotated methods) suitable for the heavy-hexagon structure and compare their logical error rates. Furthermore, we propose initialization methods to enhance the performance of magic state injection in the heavy-hexagon structure, thereby efficiently achieving logical non-Clifford gates with reduced error rates.
The surface code family is a promising approach to implementing fault-tolerant quantum computations. Universal fault-tolerance requires error-corrected non-Clifford operations, in addition to Clifford gates, and for the former, it is imperative to experimentally demonstrate additional resources known as magic states. Another challenge is to efficiently embed surface codes into quantum hardware with connectivity constraints. This work simultaneously addresses both challenges by employing a qubit-efficient rotated heavy-hexagonal surface code for IBM quantum processors (ibm_fez) and implementing the magic state injection protocol. Our work reports error thresholds for both logical bit- and phase-flip errors, of [Formula: see text] and [Formula: see text], respectively, which are higher than the threshold values previously reported with traditional embedding. The post-selection-based preparation of logical magic states [Formula: see text] and [Formula: see text] achieve fidelities of [Formula: see text] and [Formula: see text], respectively, which are both above the magic state distillation threshold. The post-selection process yields an average success rate of [Formula: see text]. Additionally, we report the minimum fidelity among injected arbitrary single logical qubit states as [Formula: see text]. Our work demonstrates the potential for realising non-Clifford logical gates by producing high-fidelity logical magic states on IBM quantum devices.
When implementing scalable fault-tolerant quantum computing using superconducting quantum processors, one of the critical challenges to overcome is the presence of defective qubits arising from fabrication and calibration imperfections. A defect on a specific qubit severely restricts the connectivity between adjacent qubits, disrupts stabilizer measurements, induces frequent detection events, and consequently inflates the logical error rate. To mitigate this issue, various strategies have been proposed, such as syndrome extraction circuits based on stabilizer folding and the construction of super-stabilizers via gauge operators. However, these methods have primarily been developed for architectures with relatively high connectivity of 3 to 4. Furthermore, experimental demonstrations showing an actual reduction in logical error rates in the presence of physical hardware defects have been lacking. In this work, we propose a defect-avoidance scheme tailored for the heavy-hexagon architecture, which features a lower connectivity of 2 to 3. While previous approaches required four measurement cycles to measure all gauge operators comprising a super-stabilizer, our proposed scheme completes all gauge measurements within only two cycles. We experimentally validate this approach on IBM quantum hardware by identifying physical defects and implementing the defect-avoidance circuits. As a result, avoiding the defect yields an approximately 10\% reduction in the logical error rate per cycle for both logical XXX and ZZZ errors. These findings demonstrate that defects in superconducting hardware can be successfully handled even under the constrained connectivity of heavy-hexagon lattices, and that defect avoidance substantially reduces logical errors on real quantum hardware.
Topological quantum error correction is a milestone in the scaling roadmap of quantum computers, which targets circuits with trillions of gates that would allow running quantum algorithms for real-world problems. The square-lattice surface code has become the workhorse to address this challenge, as it poses milder requirements on current devices both in terms of required error rates and small local connectivities. In some platforms, however, the connectivities are kept even lower in order to minimise gate errors at the hardware level, which limits the error correcting codes that can be directly implemented on them. In this work, we make a comparative study of possible strategies to overcome this limitation for the heavy-hexagonal lattice, the architecture of current IBM superconducting quantum computers. We explore two complementary strategies: the search for an efficient embedding of the surface code into the heavy-hexagonal lattice, as well as the use of codes whose connectivity requirements are naturally tailored to this architecture, such as subsystem-type and Floquet codes. Using noise models of increased complexity, we assess the performance of these strategies for IBM devices in terms of their error thresholds and qubit footprints. An optimized SWAP-based embedding of the surface code is found to be the most promising strategy towards a near-term demonstration of quantum error correction advantage.
Designs for quantum error correction depend strongly on the connectivity of the qubits. For solid-state qubits, the most straightforward approach is to have connectivity constrained to a planar graph. Practical considerations may also further restrict the connectivity, resulting in a relatively sparse graph such as the heavy-hexagonal (“heavy-hex”) architecture of current IBM Quantum devices. In such cases, it is hard to use all qubits to their full potential. Instead, in order to emulate the denser connectivity required to implement well-known quantum error-correcting codes, many qubits remain effectively unused. In this work, we show how this bug can be turned into a feature. By using the unused qubits of one code to execute another, two codes can be implemented on top of each other, allowing easy application of fault-tolerant entangling gates and measurements. We demonstrate this by realizing a surface code and a Bacon-Shor code on a 133-qubit IBM Quantum device. Using transversal controlled- X () gates and lattice surgery, we demonstrate entanglement between these logical qubits with code distance up to d = 4 and five rounds of stabilizer-measurement cycles. The nonplanar coupling between the qubits allows us to simultaneously measure the logical X X , Y Y , and Z Z observables. With this, we verify the violation of Bell’s inequality for both the d = 2 case with postselection featuring a fidelity of 94% and the d = 3 instance using only quantum error correction. Published by the American Physical Society 2024
The surface code family is a promising approach to implementing fault-tolerant quantum computations. Universal fault-tolerance quantum computing requires error-corrected nonClifford operations, in addition to Clifford gates, and for the former, it is important to experimentally demonstrate additional resources known as magic states. Another challenge is to efficiently embed surface codes into quantum hardware with connectivity constraints. This work simultaneously addresses both challenges by employing a qubit-efficient rotated heavyhexagonal surface code for IBM quantum processors (ibm_fez) and implementing the magic state injection protocol. Our work reports error thresholds for both logical bit- and phase-flip errors, of≈0.37%\approx 0.37 \%≈0.37%and≈0.31%\approx 0.31 \%≈0.31%, respectively, which are higher than the threshold values previously reported with traditional embedding. The post-selection-based preparation of logical magic states∣HL⟩\vert H_{L}\rangle∣HL​⟩and∣TL⟩\vert T_{L}\rangle∣TL​⟩achieves fidelities of0.8806±0.00020.8806 \pm 0.00020.8806±0.0002and0.8665±0.00030.8665 \pm 0.00030.8665±0.0003, respectively, which are both above the magic state distillation threshold. Our work demonstrates the potential for realising nonClifford logical gates by producing high-fidelity logical magic states on IBM quantum devices.