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arXiv:2410.06375 · Asilomar Conference on Signals, Systems and Computers (ACSSC)

An Optimized Nearest Neighbor Compliant Quantum Circuit for 5-Qubit Code

Arijit Mondal, Keshab K. Parhi

Published Oct 27, 2024• 2 citations
arXivHTMLPDF

Abstract

The five-qubit quantum error correcting code encodes one logical qubit to five physical qubits, and protects the code from a single error. It was one of the first quantum codes to be invented, and various encoding circuits have been proposed for it. In this paper, we propose a systematic procedure for optimization of encoder circuits for stabilizer codes. We start with the systematic construction of an encoder for a five-qubit code, and optimize the circuit in terms of the number of quantum gates. Our method is also applicable to larger stabilizer codes. We further propose nearest neighbor compliant (NNC) circuits for the proposed encoder using a single swap gate, as compared to three swap gates in a prior design.

DOI
10.1109/ieeeconf60004.2024.10943092

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The five-qubit quantum error correcting code encodes one logical qubit to five physical qubits, and protects the code from a single error. It was one of the first quantum codes to be invented, and various encoding circuits have been proposed for it. In this paper, we propose a systematic procedure for optimization of encoder circuits for stabilizer codes. We start with the systematic construction of an encoder for a five-qubit code, and optimize the circuit in terms of the number of quantum gates. Our method is also applicable to larger stabilizer codes. We further propose nearest neighbor compliant (NNC) circuits for the proposed encoder using a single swap gate, as compared to three swap gates in a prior design.
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Motivated by its promising applications e.g. for database search or factorization, significant progress has been made in the development of automated design methods for quantum circuits. But in order to keep up with recent physical developments in this domain, new technological constraints have to be considered. Limited interaction distance between gate qubits is one of the most common of these constraints. This led to the development of several strategies aiming at making a given quantum circuit nearest neighbor-compliant by inserting SWAP gates into the existing structure. Usually these strategies are of heuristic nature. In this work, we present an exact approach that enables nearest neighbor-compliance by inserting a minimal number of SWAP gates. Experiments demonstrate the applicability of the approach which enabled a comparison of results obtained by heuristic methods to the actual optimum.
Quantum error correction is vital for implementing universal quantum computing. A key component is the encoding circuit that maps a product state of physical qubits into the encoded multipartite entangled logical state. Known methods are typically not ``optimal'' either in terms of the circuit depth (and therefore the error burden) or the specifics of the target platform, i.e., the native gates and topology of a system. This work introduces a variational compiler for efficiently finding the encoding circuit of general quantum error-correcting codes with given quantum hardware. Focusing on the noisy intermediate-scale quantum regime, we show how to systematically compile the circuit following an optimizing process seeking to minimize the number of noisy operations that are allowed by the noisy quantum hardware or to obtain the highest fidelity of the encoded state with noisy gates. We demonstrate our method by deriving efficient encoders for logic states of the five-qubit code and the seven-qubit Steane code. We describe ways to augment the discovered circuits with error detection. Our method is applicable quite generally for compiling the encoding circuits of quantum error-correcting codes.
Quantum computers are a revolutionary class of computational platforms with applications in combinatorial and global optimization, machine learning, and other domains involving computationally hard problems. While these machines typically operate on qubits—quantum information elements that can occupy superpositions of the basis∣0⟩|0\rangle∣0⟩and∣1⟩|1\rangle∣1⟩states—recent advances have demonstrated the practical implementation of higher-dimensional quantum systems (qudits) across various hardware platforms. In these hardware realizations, the higher-order states are less stable and thus remain coherent for a shorter duration than the basis∣0⟩|0\rangle∣0⟩and∣1⟩|1\rangle∣1⟩states. Moreover, formal methods for designing efficient encoder circuits for these systems remain underexplored. This limitation motivates the development of efficient circuit techniques for qudit systems (d-level quantum systems). Previous works have typically established generating gate sets for higher-dimensional codes by generalizing the methods used for qubits. In this work, we introduce a systematic framework for optimizing encoder circuits for prime-dimension stabilizer codes. This framework is based on novel generating gate sets whose elements map directly to efficient Clifford gate sequences. We demonstrate the effectiveness of this method on key codes, achieving a 13–44% reduction in encoder circuit gate count for the qutrit (d = 3)[[9,5,3]]3[[9,5,3]]_{3}[[9,5,3]]3​,[[5,1,3]]3[[5,1,3]]_{3}[[5,1,3]]3​, and[[7,1,3]]3[[7,1,3]]_{3}[[7,1,3]]3​codes, and a 9–21% reduction for the ququint (d = 5)[[10,6,3]]5[[10,6,3]]_{5}[[10,6,3]]5​code when compared to prior work. We also achieved circuit depth reductions up to 42%.
Design and synthesis of quantum circuits have gained huge momentum during the last few years. With various physical constraint sone of the major issues is in making quantum circuits nearest neighbor complaint. The existing one and two dimensional architectures for the placement of qubits does not scale well for larger circuits. The situation thus demands for a faster approach to solve the problem. To make a quantum circuit nearest neighbor compliant, SWAP gates are inserted in the quantum gate circuit to bring the interacting qubits of a gate adjacent. We have proposed a faster method with a simple yet effective algorithm to minimize the number of SWAP gates for adjacent interactions. The time required for processing does not exceed one second even for larger benchmark circuits. The proposed method is found to reduce the number of SWAP gates on an average by 9.5% compared to the best results in previous works on 2D architectures, and by 45.7% compared to the best results on 1D architecture.