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arXiv:2407.18490 · Physical Review X

Fast and Parallelizable Logical Computation with Homological Product Codes

Qian Xu, Hengyun Zhou, Guo Zheng, Dolev Bluvstein, J. Pablo Bonilla Ataides, Mikhail D. Lukin, Liang Jiang

Published May 22, 2025• 16 citations
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Abstract

Quantum error correction is necessary to perform large-scale quantum computation but requires extremely large overheads in both space and time. High-rate quantum low-density-parity-check (qLDPC) codes promise a route to reduce qubit numbers, but performing computation while maintaining low space cost has required serialization of operations and extra time costs. In this work, we design fast and parallelizable logical gates for qLDPC codes and demonstrate their utility for key algorithmic subroutines such as the quantum adder. Our gate gadgets utilize transversal logical s between a data qLDPC code and a suitably constructed ancilla code to perform parallel Pauli product measurements (PPMs) on the data logical qubits. For hypergraph product codes, we show that the ancilla can be constructed by simply modifying the base classical codes of the data code, achieving parallel PPMs on a subgrid of the logical qubits with a lower space-time cost than existing schemes for an important class of circuits. Generalizations to 3D and 4D homological product codes further feature fast PPMs in constant depth. While prior work on qLDPC codes has focused on individual logical gates, we initiate the study of fault-tolerant compilation with our expanded set of native qLDPC code operations, constructing algorithmic primitives for preparing k -qubit Greenberger-Horne-Zeilinger states and distilling or teleporting k magic states with O ( 1 ) space overhead in O ( 1 ) and O ( k log k ) logical cycles, respectively. We further generalize this to key algorithmic subroutines, demonstrating the efficient implementation of quantum adders using parallel operations. Our constructions are naturally compatible with reconfigurable architectures such as neutral atom arrays, paving the way to large-scale quantum computation with low space and time overheads.

DOI
10.1103/physrevx.15.021065

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Quantum error correction is necessary to perform large-scale quantum computation but requires extremely large overheads in both space and time. High-rate quantum low-density-parity-check (qLDPC) codes promise a route to reduce qubit numbers, but performing computation while maintaining low space cost has required serialization of operations and extra time costs. In this work, we design fast and parallelizable logical gates for qLDPC codes and demonstrate their utility for key algorithmic subroutines such as the quantum adder. Our gate gadgets utilize transversal logical s between a data qLDPC code and a suitably constructed ancilla code to perform parallel Pauli product measurements (PPMs) on the data logical qubits. For hypergraph product codes, we show that the ancilla can be constructed by simply modifying the base classical codes of the data code, achieving parallel PPMs on a subgrid of the logical qubits with a lower space-time cost than existing schemes for an important class of circuits. Generalizations to 3D and 4D homological product codes further feature fast PPMs in constant depth. While prior work on qLDPC codes has focused on individual logical gates, we initiate the study of fault-tolerant compilation with our expanded set of native qLDPC code operations, constructing algorithmic primitives for preparing k -qubit Greenberger-Horne-Zeilinger states and distilling or teleporting k magic states with O ( 1 ) space overhead in O ( 1 ) and O ( k log k ) logical cycles, respectively. We further generalize this to key algorithmic subroutines, demonstrating the efficient implementation of quantum adders using parallel operations. Our constructions are naturally compatible with reconfigurable architectures such as neutral atom arrays, paving the way to large-scale quantum computation with low space and time overheads.
High-rate quantum low-density parity-check (qLDPC) codes encode many logical qubits with low physical-qubit overhead, but realizing efficient fault-tolerant computation on such dense encodings remains a major challenge. Generic, code-agnostic techniques such as code surgery and gate teleportation apply broadly, but are difficult to make modular, low-overhead, and fully certifiable on complex high-rate codes whose structure is left unexploited. Here we overcome these obstacles by co-designing the code together with its logical instruction set for a broad family of canonical lifted-product (LP) codes with cyclic symmetry. We show that these codes admit a canonical logical basis, in which conjugate logical operators are organized into rows and columns of cyclic orbits inherited directly from the underlying classical codes, analogous to the structure that makes hypergraph-product codes so tractable. This canonical basis enables universal logical processing using magic-state input and a constant number of reusable seed surgery gadgets---only two (resp. four) for a [[1122,148,≤20]][[1122,148,\leq 20]][[1122,148,≤20]] (resp. [[4350,1224,≤20]][[4350,1224,\leq 20]][[4350,1224,≤20]]) LP code. A fixed extractor smaller than half the data block also enables arbitrarily high-weight logical Pauli-product measurements (PPMs) while preserving the code's cyclic symmetry. These codes also enable rigorously fault-tolerant parallel logic, including PPMs across all logical qubits and magic-state injection from many surface codes into a full LP block. For example, a [[468,36,20]][[468,36,20]][[468,36,20]] (resp. [[952,112,17]][[952,112,17]][[952,112,17]]) code supports simultaneous measurements of arbitrary logically disjoint Pauli products with an ancilla overhead of roughly three (resp. four) times the data block size. These results advance the frontier of fault-tolerant quantum computation on ultra-high-rate quantum architectures.
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Quantum low-density parity-check (qLDPC) codes offer a promising route to scalable fault-tolerant quantum computing due to their substantially reduced footprint. However, these gains can be diluted at utility scale if we cannot also realize space-time efficient logical operations for relevant quantum applications. We present RASCqL, a reaction-time-limited architecture for space-time efficient complex-instruction-set quantum computation with qLDPC logic. RASCqL supports key algorithmic subroutines such as quantum arithmetic and state preparation directly within co-designed qLDPC codes, achieving 2×2\times2× to 7×7\times7× reductions in qubit footprint while maintaining space-time volume comparable to state-of-the-art transversal surface-code architectures. Unlike prior approaches that aim for versatile logical instruction sets for arbitrary circuits, RASCqL adopts an application-tailored code modification that embeds specific complex Clifford transformations useful for common subroutines as virtually implementable operations arising from code automorphisms. RASCqL further leverages parallel physical operations available in reconfigurable neutral-atom arrays to enable fast QEC cycles and high-fidelity transversal operations. At the cost of increased design complexity and specialization, RASCqL can improve end-to-end resource estimates for applications such as factoring and quantum chemistry simulation in both footprint and space-time volume under realistic physical error rates of approximately 2×10−32\times10^{-3}2×10−3 to 5×10−45\times10^{-4}5×10−4, without requiring additional hardware capabilities. These results demonstrate that qLDPC codes can serve as complex quantum logic units for useful quantum algorithms, extending their practical utility in fault-tolerant quantum computing architectures.
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Quantum low-density parity-check (QLDPC) codes are promising candidates for practical low-overhead quantum memories. For large-scale fault-tolerant quantum computation, we further need logical processing methods for QLDPC codes. In this work, we construct full extractors---surgery systems capable of measuring arbitrary logical Pauli operators on a code block---for several hypergraph product (HGP) codes. These extractors enable logical processing via Pauli-based computation (PBC) without the compilation overhead observed in prior works. Moreover, our extractors have sizes between 47%47\%47% and 80%80\%80% of the base HGP codes, and the extractor-augmented codes can be supported on fixed-connectivity hardware with maximum qubit degree ten. Our approach involves assembling many partial extractors with verifiable fault tolerance into a single full extractor. For a distance 101010 HGP code, circuit-level noise simulations yield logical measurement error rates of approximately 10−610^{-6}10−6 at a physical error rate of 0.1%0.1\%0.1%. These results demonstrate that extractor architectures, when designed in the fixed-connectivity setting, can achieve the space efficiency of QLDPC codes without introducing compilation overhead compared to surface-code PBC architectures.