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arXiv:2406.05377 · IEEE Access

Highly Versatile FPGA-Implemented Cyber Coherent Ising Machine

Toru Aonishi, Tatsuya Nagasawa, Toshiyuki Koizumi, Mastiyage Don Sudeera Hasaranga Gunathilaka, Kazushi Mimura, Masato Okada, Satoshi Kako, Y. Yamamoto

Published Jan 1, 2024• 8 citations
arXivHTMLPDF

Abstract

To solve large-scale real-world problems, attempts have been made to realize high-speed simulations of quantum Ising machines using field-programmable gate arrays (FPGAs) and to virtually realize networks with a large number of fully coupled spins, which are difficult to achieve in physical systems. We developed an FPGA-implemented cyber coherent Ising machine (cyber CIM) that is much more versatile than previous implementations using FPGAs. Our architecture is versatile because it can be applied to the open-loop CIM, which was proposed when CIM research began, to the closed-loop CIM, which has been used recently, and to the Jacobi successive over-relaxation method. By modifying the sequence control code for the calculation control module, other algorithms such as Simulated Bifurcation (SB) can also be implemented. Earlier studies on large-scale FPGA implementations of SB and CIM used binary or ternary discrete values for connections, whereas cyber CIM used single-precision floating-point format (FP32) values. In addition, cyber CIM uses Zeeman terms that are represented in FP32, which are not present in other large-scale FPGA systems. Our implementation with continuous interaction achieves$N=4096$on a single FPGA, which is comparable to the single-FPGA implementation of SB with binary interactions with$N=4096$. Cyber CIM enables applications such as code division multiple access multi-user detector and L0-norm regularization-based compressed sensing which were not possible with earlier FPGA systems, while providing superior calculation speeds, more than ten times faster than the graphic processor unit (GPU) implementation. Increasing parallelism, such as through clustering, can further enhance the calculation speed.

DOI
10.1109/access.2024.3504008

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Since many combinatorial optimization problems can be mapped onto ground-state search problems of Ising models, special-purpose machines for Ising problems have attracted intense attention. Simulated bifurcation (SB) is a recently proposed algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism underlying in the algorithm, providing an opportunity to solve the Ising problems very fast by massively parallel processing. In this work, we implement the SB algorithm on FPGAs by designing massively parallel custom circuits. We then compare the FPGA-based SB machines with a state-of-the-art machine called a coherent Ising machine (CIM), a highly optimized implementation of simulated annealing (SA), and GPU-based SB machines. SB machines with spin size of 2,048/4,096 (2K/4K) on an Arria10 GX1150 FPGA have 8,192 processing elements for the matrix-vector multiplication (MM) modules (the most computationally intensive part) and achieve computation throughput of 1,873/2,027 GMAC/s for the MM modules, outperforming 2K/4K SB machines on an Nvidia Tesla V100 GPU (113/183 GMAC/s). The 2K FPGA-SB solves all-to-all connected 2000-node MAX-CUT problem 14X (/124X) faster than the CIM (/the highly-optimized SA), with much better energy efficiency (288X better than the CIM).
Combinatorial optimization problems are economically valuable but computationally hard to solve. Many practical combinatorial optimizations can be converted to the ground-state search problems of Ising spin models. Simulated bifurcation (SB) is a quantum-inspired algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism, providing an opportunity for quickly solving those problems by massively parallel processing. In this article, we review our recent works on the design and implementation of high-performance FPGA-based accelerators for SB and their applications toward innovative real-time systems that make optimal responses to ever-changing situations. An example of such an application is an ultrafast financial transaction machine that detects the most profitable cross-currency arbitrage opportunities at microsecond speeds. Also, we show a scale-out architecture for SB-based Ising machines with all-to-all spin-spin couplings that allows continued scaling of both machine size and computational throughput by connecting multiple chips, rather than scaling up a single chip.
Ising machines are specialized computers for finding the lowest energy states of Ising spin models, onto which many practical combinatorial optimization problems can be mapped. Simulated bifurcation (SB) is a quantum-inspired parallelizable algorithm for Ising problems that enables scalable multi-chip implementations of Ising machines. However, the computational performance of a previously proposed multi-chip architecture tends to saturate as the number of chips increases for a given problem size because computation and communication are exclusive in the time domain. In this paper, we propose a streaming architecture for multi-chip implementations of SB-based Ising machines with full spin-to-spin connectivity. The data flow in in-chip computation is harmonized with the data flow in inter-chip communication, enabling the computation and communication to overlap and the communication time to be hidden. Systematic experiments demonstrate linear strong scaling of performance up to the vicinity of the ideal communication limit determined only by the latency of chip-to-chip communication. Our eight-FPGA (field-programmable gate array) cluster can compute a 32,768-spin problem with a high pipeline efficiency of 97.9%. The performance of a 79-FPGA cluster for a 100,000-spin problem, projected using a theoretical performance model validated on smaller experimental clusters, is comparable to that of a state-of-the-art 100,000-spin optical Ising machine.
Combinatorial optimization problems are economically valuable but computationally hard to solve. Many practical combinatorial optimizations can be converted to the ground-state search problems of Ising spin models. Simulated bifurcation (SB) is a quantum-inspired algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism, providing an opportunity for quickly solving those problems by massively parallel processing. In this article, we review our recent works on the design and implementation of high-performance FPGA-based accelerators for SB and their applications toward innovative real-time systems that make optimal responses to ever-changing situations. An example of such an application is an ultrafast financial transaction machine that detects the most profitable cross-currency arbitrage opportunities at microsecond speeds. Also, we show a scale-out architecture for SB-based Ising machines with all-to-all spin-spin couplings that allows continued scaling of both machine size and computational throughput by connecting multiple chips, rather than scaling up a single chip.
The coherent Ising machine is an optical processor that uses coherent laser pulses, but does not employ coherent quantum dynamics in a computational role. Core to its operation is the iterated simulation of all-to-all spin coupling via mean-field calculation in a classical FPGA coprocessor. Although it has been described as "operating at the quantum limit" and a "quantum artificial brain", interaction with the FPGA prevents the coherent Ising machine from exploiting quantum effects in its computations. Thus the question naturally arises: Can the optical portion of the coherent Ising machine be replaced with classical mean-field arithmetic? Here we answer this in the affirmative by showing that a straightforward noisy version of mean-field annealing closely matches CIM performance scaling, while running roughly 20 times faster in absolute terms.
Coherent Ising Machine (CIM) is a network of optical parametric oscillators that solve combinatorial optimization problems by finding the ground state of an Ising Hamiltonian. In CIMs, a problem arises when attempting to realize the Zeeman term because of the mismatch in size between interaction and Zeeman terms due to the variable amplitude of the optical parametric oscillator pulses corresponding to spins. There have been three approaches proposed so far to address this problem for CIM, including the absolute mean amplitude method, the auxiliary spin method, and the chaotic amplitude control (CAC) method. This paper focuses on the efficient implementation of Zeeman terms within the mean-field CIM model, which is a physics-inspired heuristic solver without quantum noise. With the mean-field model, computation is easier than with more physically accurate models, which makes it suitable for implementation in field programmable gate arrays and large-scale simulations. First, we examined the performance of the mean-field CIM model for realizing the Zeeman term with the CAC method, as well as their performance when compared to a more physically accurate model. Next, we compared the CAC method to other Zeeman term realization techniques on the mean-field model and a more physically accurate model. In both models, the CAC method outperformed the other methods while retaining similar performance.