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arXiv:2401.03817 · Quantum Science and Technology

Context-aware coupler reconfiguration for tunable coupler-based superconducting quantum computers

Leanghok Hour, Sengthai Heng, Sovanmonynuth Heng, Myeongseong Go, Youngsun Han

Published Oct 9, 2024• 3 citations
arXivHTMLPDF

Abstract

Abstract Crosstalk, caused by unwanted interactions from the surrounding environment, remains a fundamental challenge in existing superconducting quantum computers (SQCs). We propose a method for qubit placement, connectivity, and logical qubit allocation on tunable-coupler SQCs to eliminate unnecessary qubit connections and optimize resources while reducing crosstalk errors. Existing mitigation methods carry trade-offs, like increasing qubit connectivity or software-based gate scheduling. Our method, the Context-Aware COupler REconfiguration (CA-CORE) compilation method, aligns with application-specific design principles. It optimizes the qubit connections for improved SQC performance, leveraging tunable couplers. Through contextual analysis of qubit correlations, we configure an efficient coupling map considering SQC constraints. We then apply the SWAP-based Bidirectional Heuristic Search (SABRE) qubit mapping method and crosstalk-adaptive scheduling to further optimize the quantum circuit. Our architecture reduces depth by an average of 18% and 27%, and by up to 50% and 60%, compared to lattice and heavy-hex architectures, respectively. With crosstalk optimization through adaptive scheduling, we achieve performance improvements of 35%, 20%, and 160% on fully-enabled grid, lattice, and heavy-hex topologies, respectively.

DOI
10.1088/2058-9565/ad8510

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Abstract Crosstalk, caused by unwanted interactions from the surrounding environment, remains a fundamental challenge in existing superconducting quantum computers (SQCs). We propose a method for qubit placement, connectivity, and logical qubit allocation on tunable-coupler SQCs to eliminate unnecessary qubit connections and optimize resources while reducing crosstalk errors. Existing mitigation methods carry trade-offs, like increasing qubit connectivity or software-based gate scheduling. Our method, the Context-Aware COupler REconfiguration (CA-CORE) compilation method, aligns with application-specific design principles. It optimizes the qubit connections for improved SQC performance, leveraging tunable couplers. Through contextual analysis of qubit correlations, we configure an efficient coupling map considering SQC constraints. We then apply the SWAP-based Bidirectional Heuristic Search (SABRE) qubit mapping method and crosstalk-adaptive scheduling to further optimize the quantum circuit. Our architecture reduces depth by an average of 18% and 27%, and by up to 50% and 60%, compared to lattice and heavy-hex architectures, respectively. With crosstalk optimization through adaptive scheduling, we achieve performance improvements of 35%, 20%, and 160% on fully-enabled grid, lattice, and heavy-hex topologies, respectively.
One of the key challenges in current Noisy Intermediate-Scale Quantum (NISQ) computers is to control a quantum system with high-fidelity quantum gates. There are many reasons a quantum gate can go wrong - for superconducting transmon qubits in particular, one major source of gate error is the unwanted crosstalk between neighboring qubits due to a phenomenon called frequency crowding. We motivate a systematic approach for understanding and mitigating the crosstalk noise when executing near-term quantum programs on superconducting NISQ computers. We present a general software solution to alleviate frequency crowding by systematically tuning qubit frequencies according to input programs, trading parallelism for higher gate fidelity when necessary. The net result is that our work dramatically improves the crosstalk resilience of tunable-qubit, fixed-coupler hardware, matching or surpassing other more complex architectural designs such as tunable-coupler systems. On NISQ benchmarks, we improve worst-case program success rate by 13.3x on average, compared to existing traditional serialization strategies.
The design of coupler-based superconducting two-qubit gates simplifies circuit layout and alleviate frequency crowding, thereby enhancing the scalability and flexibility of quantum chips. However, in such architectures, a trade-off often exists between suppressing crosstalk and reducing gate duration, and how to achieve synergistic optimization of both remains an open challenge. To address this, this paper proposes a coupler-assisted superconducting two-qubit geometric gate scheme oriented towards crosstalk robustness. By introducing additional parametric degrees of freedom, the scheme steers the system evolution along desired trajectories, thereby flexibly avoiding crosstalk-sensitive operational regions. Numerical simulations demonstrate that the proposed scheme can effectively suppress crosstalk errors while enabling fast gate operations, and exhibits strong robustness against typical experimental imperfections such as qubit frequency drift. Moreover, even when accounting for unavoidable high-frequency oscillation terms and qubit decoherence in realistic physical systems, our crosstalk-robust two-qubit geometric gates still achieve high fidelity. This work provides a feasible pathway toward robust and efficient two-qubit gate implementation in superconducting quantum computation.
Crosstalk poses a significant challenge in quantum computing, particularly when quantum gates are executed in parallel, as qubit frequency resonance can lead to residual coupling and reduced gate fidelity. Current solutions struggle to mitigate both crosstalk and decoherence during parallel two-qubit gate operations on frequency-tunable quantum chips. To address this, we propose a crosstalk-aware mapping and gate scheduling (CAMEL) approach, designed to mitigate crosstalk and suppress decoherence by leveraging the tunable coupler’s physical properties and incorporating a pulse compensation technique. CAMEL operates within a two-step compilation framework: first, a qubit mapping strategy that considers both crosstalk and decoherence; and second, a gate timing scheduling method that prioritizes the execution of the largest possible set of crosstalk-free parallel gates, reducing overall circuit execution time. Evaluation results demonstrate CAMEL’s superior ability to mitigate crosstalk compared to crosstalk-agnostic methods, while successfully suppressing decoherence where other approaches fail. Additionally, CAMEL performs better than dynamic-frequency-aware techniques, particularly in low-complexity hardware environments.
The design of coupler-based superconducting two-qubit gates simplifies circuit layout and alleviate frequency crowding, thereby enhancing the scalability and flexibility of quantum chips. However, in such architectures, a trade-off often exists between suppressing crosstalk and reducing gate duration, and how to achieve synergistic optimization of both remains an open challenge. To address this, this paper proposes a coupler-assisted superconducting two-qubit geometric gate scheme oriented towards crosstalk robustness. By introducing additional parametric degrees of freedom, the scheme steers the system evolution along desired trajectories, thereby flexibly avoiding crosstalk-sensitive operational regions. Numerical simulations demonstrate that the proposed scheme can effectively suppress crosstalk errors while enabling fast gate operations, and exhibits strong robustness against typical experimental imperfections such as qubit frequency drift. Moreover, even when accounting for unavoidable high-frequency oscillation terms and qubit decoherence in realistic physical systems, our crosstalk-robust two-qubit geometric gates still achieve high fidelity. This work provides a feasible pathway toward robust and efficient two-qubit gate implementation in superconducting quantum computation.
To reduce circuit depth when executing Quantum algorithms, it is necessary to maximize qubit connectivity on a near-term quantum processor. While addressing this, we also need to ensure high gate fidelity, suppression of unwanted ZZ cross-talk, a compact layout footprint, and minimal control hardware complexity to support scalability. In current superconducting quantum chips, fixed coupling is used as it is easier to scale, but it is limited by unwanted static ZZ interaction during single qubit operations, which degrades system performance. To overcome these challenges, we have introduced a first-of-its-kind hybrid tunable-coupling architecture that connects four fixed-frequency transmon qubits using a single coupler. This hybrid coupler uses off-resonant Stark drives to tune ZZ strength between qubit pairs. Experimentally backed simulation results indicate that our proposed hybrid design maximizes the qubit connectivity while reducing control overhead. This design achieves a near 20% reduction in circuit depth compared to IBM's Heavy-Hexagonal layout, showing its potential for scalability.
Scaling superconducting quantum processors requires interconnects that provide both non-local connectivity and parallel entangling operations. While current quantum routers offer greater connectivity than nearest-neighbour topologies, their support for parallel, independently addressable two-qubit gates remains fundamentally limited, imposing severe compilation overheads that constitute a critical bottleneck. Here we introduce a bus-based reconfigurable quantum router that enables parallel controlled-ZZZ (CZ) gates for modular superconducting processors. Constructed from a flux-tunable SQUID network, the router selectively connects interface qubits to two shared buses, allowing destructive interference to suppress idle interactions while supporting two disjoint CZ gates in parallel. Full-system Hamiltonian simulations yield parallel-gate infidelities ranging from 7.9×10−47.9\times10^{-4}7.9×10−4 to 1.8×10−31.8\times10^{-3}1.8×10−3 under the operating conditions considered, and an open-system analysis identifies the coherence requirements for high-fidelity operation. We further assess the circuit-level consequences using hardware-aware compilation and resource-constrained scheduling. For the 36-qubit quantum Fourier transform (QFT), QAOA-MaxCut, and random-pairing circuits, the router reduces the median SWAP count by up to 34%34\%34% and the native CZ count by up to 20%20\%20% relative to a matched two-dimensional grid. Circuit-depth reductions are workload-dependent, reaching 20%20\%20% for QAOA-MaxCut but remaining negligible for the QFT despite its lower gate count. These results show that enhanced connectivity and schedulable parallelism provide complementary benefits for connectivity-intensive algorithms, establishing the router as a compiler-visible hardware resource and providing a scalable architectural pathway toward constructing highly connected modular superconducting quantum processors.