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arXiv:2312.15467 · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

FPGA-Placement via Quantum Annealing

Thore Gerlach, Stefan Knipp, David Biesner, Stelios Emmanouilidis, Klaus Hauber, Nico Piatkowski

Published Apr 1, 2024• 2 citations
arXivHTMLPDF

Abstract

In this work we explore the use of quantum computers in solving the NP-hard placement problem of the Field-Programmable Gate Array (FPGA) implementation phase and introduce a novel approach suited for current quantum hardware sizes. Adiabatic quantum computing (AQC), with its capability to traverse expansive solution spaces, is a good fit for addressing this combinatorial problem with its exponentially large solution space. Instead of solving a single the whole problem at once, we re-formulate the placement problem as a series of so called quadratic unconstrained binary optimization (QUBO) problems which are subsequently solved via AQC. Our novel formulation facilitates a straight-forward integration of design constraints. Moreover, the size of the sub-problems can be conveniently adapted to the available hardware capabilities. Beside the sole proposal of a novel method, we ask whether contemporary quantum hardware is resilient enough to find placements for real-world-sized FPGAs. A numerical evaluation on a D-Wave Advantage 5.4 quantum annealer suggests that the answer is in the affirmative.

DOI
10.1145/3626202.3637619

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In this work we explore the use of quantum computers in solving the NP-hard placement problem of the Field-Programmable Gate Array (FPGA) implementation phase and introduce a novel approach suited for current quantum hardware sizes. Adiabatic quantum computing (AQC), with its capability to traverse expansive solution spaces, is a good fit for addressing this combinatorial problem with its exponentially large solution space. Instead of solving a single the whole problem at once, we re-formulate the placement problem as a series of so called quadratic unconstrained binary optimization (QUBO) problems which are subsequently solved via AQC. Our novel formulation facilitates a straight-forward integration of design constraints. Moreover, the size of the sub-problems can be conveniently adapted to the available hardware capabilities. Beside the sole proposal of a novel method, we ask whether contemporary quantum hardware is resilient enough to find placements for real-world-sized FPGAs. A numerical evaluation on a D-Wave Advantage 5.4 quantum annealer suggests that the answer is in the affirmative.
Field-Programmable Gate Arrays (FPGAs) have become indispensable components in modern computing, providing adaptable and reconfigurable hardware platforms. FPGA-based accelerators offer promising avenues for advancements in diverse fields such as real-time data processing, machine learning, and cryptography. However, optimizing the spatial arrangement of functional blocks on an FPGA, known as placement, presents a challenging task due to its NP-hard nature, necessitating sophisticated algorithms for efficient solutions. Enhancing the placement process directly translates to reduced resource utilization during implementation. Quantum computing (QC) presents a promising approach for tackling such combinatorial problems by exploring vast solution spaces. In this paper, we propose a novel approach to the placement problem, re-formulating it as a series of quadratic unconstrained binary optimization (QUBO) problems, which we then solve using QC. Our novel formulation allows for straightforward integration of design constraints and enables the adaptation of sub-problem sizes to match hardware capabilities. Alongside presenting our method, we also investigate the resilience of contemporary quantum hardware in finding placements for real-world-sized FPGAs. A numerical assessment conducted on a D-Wave Advantage 5.4 quantum annealer indicates that the answer is indeed positive.
To run an algorithm on a quantum computer, one must choose an assignment from logical qubits in a circuit to physical qubits on quantum hardware. This task of initial qubit placement, or qubit allocation, is especially important on present-day quantum computers which have a limited number of qubits, connectivity constraints, and varying gate fidelities. In this work we formulate and implement the qubit placement problem as a quadratic, unconstrained binary optimization (QUBO) problem and solve it using simulated annealing to obtain a spectrum of initial placements. Compared to contemporary allocation methods available in t|ket$\rangle $ and Qiskit, the QUBO method yields allocations with improved circuit depth for $>$50% of a large set of benchmark circuits, with many also requiring fewer CX gates.
Quantum annealing device has shown a great potential in solving discrete problems that are theoretically and empirically hard. Boolean Satisfiability (SAT) problem, determining if there is an assignment of variables that satisfies a given Boolean function, is the first proven NP-complete problem widely used in various domains. Here, we present a novel mapping of the SAT problem to the quadratic unconstrained binary optimization problem (QUBO), and further develop a tool flow embedding the proposed QUBO to the architecture of the commercialized quantum computer D-Wave. By leveraging electronic design automation techniques including synthesis, placement and routing, this is not only the first work providing the detail flow that embeds the QUBO, but also a technique scalable for real world applications and some hard SAT problems with over 6000 variables in QUBO. Based on our results, we discuss the challenges in solving SAT using the current generation of annealing device, and explore the problem solving capability of future quantum annealing computers.
This study introduces an innovative application of Parallel Quantum Annealing (PQA) to concurrently solve multiple NP-hard problems on a quantum annealer, leveraging unused qubits on D-Wave's Pegasus architecture to enhance efficiency and accuracy. While parallel execution of different problems on the same quantum annealing device has been previously explored, our application extends the current PQA method, which typically solves a single problem multiple times or different problems with minor embedded combinatorial optimization. This study primarily focuses on three NP-hard problems relevant to integrated circuit design: the Graph Coloring Problem (GCP), the Minimum Vertex Cover Problem (MVCP), and the Graph Partitioning Problem (GPP). After formulating these problems as Quadratic Unconstrained Binary Optimization (QUBO), they were embedded into the D-Wave quantum annealing machine, and the annealing process was run on the combined QUBO. The results were subsequently decoded into individual problems. Our results, quantified via the Time-To-Target (TTT) metric, showcased enhanced efficiency and accuracy in reaching target solutions, indicating a substantial improvement over traditional Quantum Annealing (QA) and Simulated Annealing (SA) methods. The research illustrates the potential of quantum computing for solving complex real-world problems more efficiently and emphasizes the importance of leveraging all available qubits in quantum annealers. The findings can significantly contribute to the development and optimization of quantum computing methods and have broad application implications, particularly in areas where NP-hard problems are prevalent.
We present experiments in solving combinatorial optimization and constraint satisfaction problems by means of Quantum Annealing. We describe how to model classic constraint problems such as N-queens and Magic Square as well as hard combinatorial problems such as the Costas Array Problem or the Quadratic Assignment Problem in terms of QUBO (Quadratic Unconstrained Binary Optimization). QUBO is the input language of quantum computers based on quantum annealing such as the D-Wave systems and of the ”quantum-inspired” but classical devices such as Fujitsu’s Digital Annealing Unit or Hitachi’s CMOS Annealing Machine. We present preliminary results for solving these combinatorial optimization and constraint satisfaction problems by implementation on the D-Wave quantum computer.
Quantum annealing computers are designed to produce high-quality solutions to optimization problems that can be formulated as quadratic unconstrained binary optimization (QUBO) problems. While most of the well known NP-hard problems can easily be represented as quadratic binary problems, such formulations usually contain constraints that have to be added as penalties to the objective function in order to obtain QUBOs. In this paper, we propose a method based on finite automaton representation of the constraints for generating penalty implementations for them, which uses fewer qubits than the alternatives and is general enough to be applied to a whole class of constraints.