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arXiv:2312.14060 · Physical Review Research

Fault-tolerant quantum architectures based on erasure qubits

Shouzhen Gu, Alex Retzker, Aleksander Kubica

Published Mar 6, 2025• 14 citations
arXivHTMLPDF

Abstract

The overhead of quantum error correction (QEC) poses a major bottleneck for realizing fault-tolerant computation. To reduce this overhead, we exploit the idea of erasure qubits, relying on an efficient conversion of the dominant noise into erasures at known locations. We start by introducing a formalism for QEC schemes with erasure qubits and express the corresponding decoding problem as a matching problem. Then, we propose and optimize QEC schemes based on erasure qubits and the recently introduced Floquet codes. Our schemes are well suited for superconducting circuits, being compatible with planar layouts. We numerically estimate the memory thresholds for the circuit noise model that includes spreading (via entangling operations) and imperfect detection of erasures. Our results demonstrate that, despite being slightly more complex, QEC schemes based on erasure qubits can significantly outperform standard approaches.

DOI
10.1103/physrevresearch.7.013249

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The overhead of quantum error correction (QEC) poses a major bottleneck for realizing fault-tolerant computation. To reduce this overhead, we exploit the idea of erasure qubits, relying on an efficient conversion of the dominant noise into erasures at known locations. We start by introducing a formalism for QEC schemes with erasure qubits and express the corresponding decoding problem as a matching problem. Then, we propose and optimize QEC schemes based on erasure qubits and the recently introduced Floquet codes. Our schemes are well suited for superconducting circuits, being compatible with planar layouts. We numerically estimate the memory thresholds for the circuit noise model that includes spreading (via entangling operations) and imperfect detection of erasures. Our results demonstrate that, despite being slightly more complex, QEC schemes based on erasure qubits can significantly outperform standard approaches.
Erasure qubits offer a promising avenue toward reducing the overhead of quantum error correction (QEC) protocols. However, they require additional operations, such as erasure checks, that may add extra noise and increase the run-time of QEC protocols. To assess the benefits provided by erasure qubits, we focus on the performance of the surface code as a quantum memory. In particular, we analyze various erasure check schedules, find the correctable regions in the phase space of error parameters, and probe the subthreshold scaling of the logical error rate. We then consider a realization of erasure qubits in the superconducting hardware architectures via dual-rail qubits. We use the standard transmon-based implementation of the surface code as the performance benchmark. Our results indicate that QEC protocols with erasure qubits can outperform the ones with state-of-the-art transmons, even in the absence of precise information about the locations of erasure errors.
Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction. A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient quantum error correction, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers.
Abstract Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction (QEC). A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient QEC, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers.
The threshold theorem indicates that if errors are all local and their rates are below a certain threshold, it is possible to implement large scale quantum computation with arbitrarily small error based on active quantum error correction (QEC). However, most fault-tolerant quantum computation (FTQC) schemes require enormous overhead to achieve this rate by increasing either the concatenation levels for concatenated codes or the distance (hence the size) for topological codes. As a result, a logical qubit is usually encoded in more than thousands of physical qubits, even when the error rate is below the threshold. In this thesis, we try to reduce the resource overhead of FTQC. We first study a quantum computation scheme using clouds of atoms trapped on atomic chips. It suggests that this scheme is robust to noise to some extent and has potential to be scalable. Secondly, we propose a FTQC scheme of encoding many logical qubits into large code blocks. The error performance of such scheme is numerically studied. Preparation of various ancilla states necessary for computation is also explored. Thirdly, we explore the idea of introducing energy gap to suppress thermal noise on each qubit. We show that fault-tolerant holonomic quantum computation (HQC) can be implemented in stabilizer codes with the existence of such energy protection. Especially, we studied fault-tolerant HQC in surface codes in detail. This scheme opens the possibility for self-correcting quantum computation in 2D lattice.
Recently, significant effort has been devoted towards designing erasure qubits in which dominant physical noise excites detectable leakage states that can be returned to the qubit subspace. Interest in these erasure qubits has been driven by studies showing that the requirements for fault-tolerant quantum error correction are significantly relaxed when noise in every gate operation is dominated by erasures. However, these studies assume perfectly accurate erasure checks after every gate operation which generally come with undesirable time and hardware overhead costs. In this work, we investigate the consequences of using an imperfect but overhead-efficient erasure check for fault-tolerant quantum error correction with the surface code. We show that, under physically reasonable assumptions on the imperfect erasure checks, the threshold error rate is still at least over twice that for Pauli noise. We also study the impact of imperfect erasure checks on the effective error distance and find that it degrades the effective distance under a general error model in which a qubit suffers from depolarizing noise when interacting with a leaked qubit. We then identify a more restrictive but realistic noise model for a qubit that interacts with a leaked qubit, under which the effective error distance is twice that for Pauli noise. We apply our analysis to recently proposed superconducting dual-rail erasure qubits and show that achieving good-performance surface code quantum memories with relaxed system requirements is possible.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit. We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.