We introduce the Trapped-Ion Surface Code Compiler (TISCC), a software tool that generates circuits for a universal set of surface code patch operations in terms of a native trapped-ion gate set. To accomplish this, TISCC manages an internal representation of a trapped-ion system where a repeating pattern of trapping zones and junctions is arranged in an arbitrarily large rectangular grid. Surface code operations are compiled by instantiating surface code patches on the grid and using methods to generate transversal operations over data qubits, rounds of error correction over stabilizer plaquettes, and/or lattice surgery operations between neighboring patches. Beyond the implementation of a basic surface code instruction set, TISCC contains corner movement functionality and a patch translation that is implemented using ion movement alone. Except in the latter case, all TISCC functionality is extensible to alternative grid-like hardware architectures. TISCC output has been verified using the Oak Ridge Quasi-Clifford Simulator (ORQCS).We introduce the Trapped-Ion Surface Code Compiler (TISCC), a software tool that generates circuits for a universal set of surface code patch operations in terms of a native trapped-ion gate set. To accomplish this, TISCC manages an internal representation of a trapped-ion system where a repeating pattern of trapping zones and junctions is arranged in an arbitrarily large rectangular grid. Surface code operations are compiled by instantiating surface code patches on the grid and using methods to generate transversal operations over data qubits, rounds of error correction over stabilizer plaquettes, and/or lattice surgery operations between neighboring patches. Beyond the implementation of a basic surface code instruction set, TISCC contains corner movement functionality and a patch translation that is implemented using ion movement alone. Except in the latter case, all TISCC functionality is extensible to alternative grid-like hardware architectures. TISCC output has been verified using the Oak Ridge Quasi-Clifford Simulator (ORQCS).

Jan 1, 20240 citations

Advanced Resource Estimation through Lattice Surgery Compilation and Logical Error Modeling

Tyler LeBlond, Ryan S. Bennink

In the early fault-tolerant quantum computing era, it is desirable to accurately capture resource estimates for practical quantum circuit execution on future fault-tolerant quantum processors. While several open-source resource estimation tools currently exist, they fall short of realism in multiple facets: first, they do not rely on explicit compilation, thus necessitating several simplifying assumptions. Second, they rely on one-size-fits-all logical error rate formulae for all members of their logical instruction set. To properly account for the resource overhead of fault-tolerance, a comprehensive strategy for compiling logical circuits into fault-tolerant operations on a hardware-mapped quantum error-correcting code is required. In the case of the surface code, explicit compilation enables resource estimation for schemes that do not assume a constant rate of magic state consumption and the more realistic computation of total logical error based on active hardware tiles. This poster will focus on ORNL's efforts toward developing compiler-based resource estimation for a surface code mapping onto a hypothetical trappedion QCCD architecture. To this end, two open-source compilers and a simulator have been developed. First, we use a significantly-revised Lattice Surgery Compiler (LSC) to compile logical circuits into surface code primitives acting on abstract hardware tiles. Second, the Trapped-Ion Surface Code Compiler (TISCC) compiles these primitives into native trappedion hardware gates acting on trapping zones. Finally, we use the Oak Ridge Quasi-Clifford Simulator (ORQCS) to evaluate the fault-tolerance of TISCC circuits under realistic trappedion QCCD noise assumptions. We describe how this end-to-end fault-tolerance compilation and simulation capability enables advanced resource estimation.In the early fault-tolerant quantum computing era, it is desirable to accurately capture resource estimates for practical quantum circuit execution on future fault-tolerant quantum processors. While several open-source resource estimation tools currently exist, they fall short of realism in multiple facets: first, they do not rely on explicit compilation, thus necessitating several simplifying assumptions. Second, they rely on one-size-fits-all logical error rate formulae for all members of their logical instruction set. To properly account for the resource overhead of fault-tolerance, a comprehensive strategy for compiling logical circuits into fault-tolerant operations on a hardware-mapped quantum error-correcting code is required. In the case of the surface code, explicit compilation enables resource estimation for schemes that do not assume a constant rate of magic state consumption and the more realistic computation of total logical error based on active hardware tiles. This poster will focus on ORNL's efforts toward developing compiler-based resource estimation for a surface code mapping onto a hypothetical trappedion QCCD architecture. To this end, two open-source compilers and a simulator have been developed. First, we use a significantly-revised Lattice Surgery Compiler (LSC) to compile logical circuits into surface code primitives acting on abstract hardware tiles. Second, the Trapped-Ion Surface Code Compiler (TISCC) compiles these primitives into native trappedion hardware gates acting on trapping zones. Finally, we use the Oak Ridge Quasi-Clifford Simulator (ORQCS) to evaluate the fault-tolerance of TISCC circuits under realistic trappedion QCCD noise assumptions. We describe how this end-to-end fault-tolerance compilation and simulation capability enables advanced resource estimation.

IEEE International Conference on Quantum Computing and Engineering (QCE)Sep 15, 20240 citations

A High Performance Compiler for Very Large Scale Surface Code Computations

George Watkins, Hoang Minh Nguyen, Keelan Watkins +3 more

We present the first high performance compiler for very large scale quantum error correction: it translates an arbitrary quantum circuit to surface code operations based on lattice surgery. Our compiler offers an end to end error correction workflow implemented by a pluggable architecture centered around an intermediate representation of lattice surgery instructions. Moreover, the compiler supports customizable circuit layouts, can be used for quantum benchmarking and includes a quantum resource estimator. The compiler can process millions of gates using a streaming pipeline at a speed geared towards real-time operation of a physical device. We compiled within seconds 80 million logical surface code instructions, corresponding to a high precision Clifford+T implementation of the 128-qubit Quantum Fourier Transform (QFT).We present the first high performance compiler for very large scale quantum error correction: it translates an arbitrary quantum circuit to surface code operations based on lattice surgery. Our compiler offers an end to end error correction workflow implemented by a pluggable architecture centered around an intermediate representation of lattice surgery instructions. Moreover, the compiler supports customizable circuit layouts, can be used for quantum benchmarking and includes a quantum resource estimator. The compiler can process millions of gates using a streaming pipeline at a speed geared towards real-time operation of a physical device. We compiled within seconds 80 million logical surface code instructions, corresponding to a high precision Clifford+T implementation of the 128-qubit Quantum Fourier Transform (QFT).

arXiv:2302.02459QuantumMay 22, 202426 citations

A Folded Surface Code Architecture for 2D Quantum Hardware

Zhu Sun, Zhenyu Cai

Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from $\mathcal{O}(d)$ in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal $S$ gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from $\mathcal{O}(d)$ in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal $S$ gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.

quant-pharXiv:2601.19823Jan 28, 20260 citations

A Resource Allocating Compiler for Lattice Surgery

Alan Robertson, Gao, Haowen, Yuval R. Sanders

The emerging field of quantum resource estimation is aimed at providing estimates of the hardware requirements (`quantum resources') needed to execute a useful, fault-tolerant quantum computation. Given that quantum computers are intended to compete with supercomputers, useful quantum computations are likely to involve the use of millions of qubits and error correction clock cycles. The compilation and benchmarking of these circuits depends on placement and routing algorithms, which are infeasible to construct at scale by hand. We offer a compiler that transforms a quantum circuit into a sequence of lattice surgery operations. The compiler manages memory in terms of surface code patches and costs the space-time volume and cycle counts of the input circuits. These compiled lattice surgery objects are then recursively repurposed as gates for larger scale compilations. Our code is available on GitHub under a permissive software license and we welcome community contributions.The emerging field of quantum resource estimation is aimed at providing estimates of the hardware requirements (`quantum resources') needed to execute a useful, fault-tolerant quantum computation. Given that quantum computers are intended to compete with supercomputers, useful quantum computations are likely to involve the use of millions of qubits and error correction clock cycles. The compilation and benchmarking of these circuits depends on placement and routing algorithms, which are infeasible to construct at scale by hand. We offer a compiler that transforms a quantum circuit into a sequence of lattice surgery operations. The compiler manages memory in terms of surface code patches and costs the space-time volume and cycle counts of the input circuits. These compiled lattice surgery objects are then recursively repurposed as gates for larger scale compilations. Our code is available on GitHub under a permissive software license and we welcome community contributions.

arXiv:2506.04620Jun 5, 20250 citations

Architecting Scalable Trapped Ion Quantum Computers using Surface Codes

Scott Jones, Prakash Murali

Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.

arXiv:2510.23519International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)Mar 10, 20260 citations

\mathcal{O}(d)

in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal

S

gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.