Abstract Quantum Random Access Memory (QRAM) is a critical component for enabling data queries in superposition, which is the cornerstone of quantum algorithms. Among various QRAM architectures, the bucket‐brigade model stands out due to its noise resilience. This study presents a hardware‐efficient native gate set for implementing bucket‐brigade QRAM on superconducting platforms. The experimental feasibility of the proposed gate set is demonstrated, showing high fidelity and reduced complexity. By leveraging the complementary control property in QRAM, the approach directly substitutes the conventional gates with the new gate set, eliminating decomposition overhead and significantly reducing circuit depth and gate count.
Abstract Quantum Random Access Memory (QRAM) is a critical component for enabling data queries in superposition, which is the cornerstone of quantum algorithms. Among various QRAM architectures, the bucket‐brigade model stands out due to its noise resilience. This study presents a hardware‐efficient native gate set for implementing bucket‐brigade QRAM on superconducting platforms. The experimental feasibility of the proposed gate set is demonstrated, showing high fidelity and reduced complexity. By leveraging the complementary control property in QRAM, the approach directly substitutes the conventional gates with the new gate set, eliminating decomposition overhead and significantly reducing circuit depth and gate count.
Quantum random access memory (QRAM) enables efficient classical data access for quantum computers -- a prerequisite for many quantum algorithms to achieve quantum speedup. Despite various proposals, the experimental realization of QRAM remains largely unexplored. Here, we experimentally investigate the circuit-based bucket-brigade QRAM with a superconducting quantum processor. To facilitate the experimental implementation, we introduce a hardware-efficient gate decomposition scheme for quantum routers, which effectively reduces the depth of the QRAM circuit by more than 30% compared to the conventional controlled-SWAP-based implementation. We further propose an error mitigation method to boost the QRAM query fidelity. With these techniques, we are able to experimentally implement the QRAM architectures with two and three layers, achieving query fidelities up to 0.800 ± 0.026 and 0.604$\pm$0.005, respectively. Additionally, we study the error propagation mechanism and the scalability of our QRAM implementation, providing experimental evidence for the noise resilience nature of the bucket-brigade QRAM architecture. Our results highlight the potential of superconducting quantum processors for realizing a scalable QRAM architecture.
Quantum random access memory (QRAM)—memory which stores classical data but allows queries to be performed in superposition—is required for the implementation of numerous quantum algorithms. While naive implementations of QRAM are highly susceptible to decoherence and hence not scalable, it has been argued that the bucket-brigade QRAM architecture [Giovannetti et al., Phys. Rev. Lett. 100, 160501 (2008)] is highly resilient to noise, with the infidelity of a query scaling only logarithmically with the memory size. In prior analyses, however, this favorable scaling followed directly from the use of contrived noise models, thus leaving open the question of whether experimental implementations would actually enjoy the purported scaling advantage. In this work, we study the effects of decoherence on QRAM in full generality. Our main result is a proof that this favorable infidelity scaling holds for arbitrary error channels (including, e.g., depolarizing noise and coherent errors). Our proof identifies the origin of this noise resilience as the limited entanglement among the memory’s components, and it also reveals that significant architectural simplifications can be made while preserving the noise resilience. We verify these results numerically using a novel classical algorithm for the efficient simulation of noisy QRAM circuits. Our findings indicate that QRAM can be implemented with existing hardware in realistically noisy devices, and that high-fidelity queries are possible without quantum error correction. Furthermore, we also prove that the benefits of the bucket-brigade architecture persist when quantum error correction is used, in which case the scheme offers improved hardware efficiency and resilience to logical errors.
Quantum random access memory (QRAM)-memory which stores classical data but allows queries to be performed in superposition-is required for the implementation of numerous quantum algorithms.While naive implementations of QRAM are highly susceptible to decoherence and hence not scalable, it has been argued that the bucket-brigade QRAM architecture [Giovannetti et al., Phys. Rev. Lett. 100, 160501 (2008)] is highly resilient to noise, with the infidelity of a query scaling only logarithmically with the memory size.In prior analyses, however, this favorable scaling followed directly from the use of contrived noise models, thus leaving open the question of whether experimental implementations would actually enjoy the purported scaling advantage.In this work, we study the effects of decoherence on QRAM in full generality.Our main result is a proof that this favorable infidelity scaling holds for arbitrary error channels (including, e.g., depolarizing noise and coherent errors).Our proof identifies the origin of this noise resilience as the limited entanglement among the memory's components, and it also reveals that significant architectural simplifications can be made while preserving the noise resilience.We verify these results numerically using a novel classical algorithm for the efficient simulation of noisy QRAM circuits.Our findings indicate that QRAM can be implemented with existing hardware in realistically noisy devices, and that high-fidelity queries are possible without quantum error correction.Furthermore, we also prove that the benefits of the bucket-brigade architecture persist when quantum error correction is used, in which case the scheme offers improved hardware efficiency and resilience to logical errors.
Quantum routers (QRouters) are essential components of bucket-brigade quantum random access memory (QRAM), enabling quantum applications such as Grover’s search and quantum machine learning. Despite significant theoretical advances, achieving scalable and coherent QRouters experimentally remains challenging. Here, we demonstrate coherent quantum routers using a superconducting quantum processor, laying a practical foundation for scalable QRAM systems. The quantum router at the core of our implementation utilizes the transition composite gate scheme, wherein auxiliary energy levels temporarily mediate conditional interactions. By leveraging two-qubit primitives in its construction, the quantum router preserves straightforward initialization and calibration while significantly reducing circuit depth and duration relative to traditional gate-based decompositions. Moreover, by encoding routing addresses in the nonadjacent qutrit states | 0 ⟩ and | 2 ⟩ , our design inherently enables erasure-detection capability, providing efficient postselection to mitigate routing errors. Experimentally, we achieve an average fidelity of 94.8% across three individual QRouters, and we validate scalability through a two-layer quantum routing network achieving a fidelity of 82.4%. Our results represent a significant advancement in quantum routing technology, providing enhanced fidelity, built-in error resilience, and practical scalability crucial for the development of future QRAM and large-scale quantum computing architectures.
The preparation of data in quantum states is a critical component in the design of quantum algorithms. The cost of this step can significantly limit the realization of quantum advantage in domains such as machine learning, finance, and chemistry. One of the main approaches to achieve efficient state preparation is through the use of Quantum Random Access Memory (QRAM), a theoretical device for coherent data access with several proposed hardware implementations. In this work, we present a framework that integrates the hardware model of the Bucket Brigade QRAM (BBQRAM) with the classical data structure of the Segment Tree to achieve efficient state preparation. We introduce a memory layout that embeds a segment tree within BBQRAM memory cells by preserving the segment tree's hierarchy and supporting data retrieval in logarithmic time via specialized access primitives. We demonstrate that our method encodes a matrix A∈RM×N in a quantum register of Θ(log2(MN)) qubits in O(log22(MN)) time, {requiring a constant number of working qubits (under fixed precision) and O(MN) memory cells within the BBQRAM architecture.} We further illustrate the method through a numerical example. This framework provides theoretical support for quantum algorithms that assume negligible data loading overhead and establishes a foundation for designing classical-to-quantum encoding algorithms that are aware of the underlying hardware QRAM architecture.
Quantum random-access memory (QRAM) enables coherent queries to classical data. However, the O(N) qubits required for a memory with N=2n addresses make QRAM appear vulnerable to noise. Though bucket-brigade routing provides intrinsic noise resilience to reduce the error in QRAM, improving the fidelity of QRAM queries is still an important and challenging problem. We introduce a low-overhead protection framework for bucket-brigade QRAM with two complementary components. First, we propose a one-fault-tolerant repeat-until-success logical controlled-SWAP gate using the [[4,2,2]] code under erasure noise channel. Interleaved erasure checks and local recovery correct every single erasure, so the leading logical failure probability is second order in the physical erasure error rates. Second, we exploit validity constraints of bucket-brigade routing to define local parity checks directly on the router states, without adding extra data qubits to create code redundancy. Under bit-flip noise, minimum-weight perfect matching with noiseless syndrome measurements corrects single interior faults, while open spatial boundaries retain a first-order contribution in the residual bit-flip rate. Monte Carlo simulations confirm quadratic suppression for the protected controlled-SWAP and improved depth scaling for decoded QRAM router-state snapshots. The two codes admit a concatenated realization in which the inner code supplies erasure protection and the outer code optionally corrects interior logical bit flips. Together, these results show how routing constraints and a protected non-Clifford routing gate can improve QRAM reliability under biased and erasure-dominant noise.