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arXiv:2303.04798 · Quantum

Hierarchical memories: Simulating quantum LDPC codes with local gates

Christopher A. Pattison, Anirudh Krishna, John P. Preskill

Published May 5, 2025• 20 citations
arXivHTMLPDF

Abstract

Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of [[N,K,D]] codes, referred to as hierarchical codes, that encode a number of logical qubits K=Ω(N/log⁡(N)2) . The Nth element of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the corresponding syndrome-extraction circuit and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance D(N) . We present a bilayer architecture for implementing the syndrome-extraction circuit, and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code.

DOI
10.22331/q-2025-05-05-1728

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Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of [[N,K,D]] codes, referred to as hierarchical codes, that encode a number of logical qubits K=Ω(N/log⁡(N)2) . The Nth element of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the corresponding syndrome-extraction circuit and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance D(N) . We present a bilayer architecture for implementing the syndrome-extraction circuit, and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code.
High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a planar grid of qubits with either square or hexagonal connectivity. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the roles of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 40 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by a factor of 100 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.
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Abstract We propose and analyze a hierarchical quantum error correction (QEC) scheme that concatenates hypergraph product (HGP) codes with rotated surface codes and that is compatible with quantum computers with only nearest-neighbor interactions. The outer code employs (3,4)-random HGP codes, known for their constant encoding rate and favorable distance scaling, while the inner code consists of a rotated surface code with distance 5, allowing hardware compatibility through lattice surgery. To address the decoding bottleneck, we utilize a soft-decision decoding strategy that combines belief propagation with ordered statistics decoding, enhanced by a syndrome-conditioned logical error probability computed via a tailored lookup table for the inner code. Numerical simulations under a code capacity noise model demonstrate that our hierarchical codes achieve logical error suppression below the threshold. Furthermore, we derive explicit conditions under which the proposed codes surpass surface codes as a QEC code in both qubit efficiency and error rate. In particular, for the size parameter s≥4s \ge 4s≥4 (which corresponds to 16 logical qubits) and the distance d≥25d\ge 25d≥25, our construction outperforms the rotated surface code in practical regimes with physical error rates around or less than 10−210^{-2}10−2. These results suggest that concatenated quantum low-density parity-check surface architectures can offer a scalable and resource-efficient path toward near-term fault-tolerant quantum computation.
Constant-rate quantum low-density parity-check (LDPC) codes promise fault-tolerant quantum computation with constant spatial overhead in the asymptotic limit. Nonetheless, discovering finite-length code instances with good practical performance remains challenging. We introduce a new family of quantum LDPC codes with design rate 1/51/51/5 and check weight 999 that approaches the teraquop memory regime per qubit-round with several hundred physical qubits, under idling-free circuit-level noise of strength 0.1%0.1\%0.1% and GPU-accelerated Relay-belief-propagation (Relay-BP) decoding with average latencies around 1-2 ms, a regime relevant to trapped-ion and neutral-atom processors. The construction involves the balanced product of classical LDPC codes with design rate 1/21/21/2 that share non-abelian Zℓ⋊Zm\mathbb{Z}_\ell \rtimes \mathbb{Z}_mZℓ​⋊Zm​ group symmetries, which may be of independent interest for classical error correction. We build syndrome extraction circuits tailored to reconfigurable atom arrays using a simple greedy scheduler, with single-round rearrangement times around 30-60 ms using present hardware specifications, and substantial room for future improvements. We also construct logical Pauli bases that are equivariant with respect to the group symmetry, which can significantly compress the design space for code surgery. Together, these results further advance the practicality of constant-rate quantum LDPC codes for near-term, fault-tolerant quantum computers.
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High qubit overhead is a key bottleneck for fault-tolerant quantum computation. Quantum low-density parity-check (qLDPC) codes offer high encoding efficiency but typically require non-local connectivity in every syndrome extraction cycle, incurring additional physical errors and implementation complexity. We introduce a hierarchical logical processor (HLP) architecture that implements a high-rate quantum CSS code with distance-d0d_{0}d0​ rotated surface codes (RSC), allowing long-range connectivity to be used only once every Θ(d0)Θ(d_{0})Θ(d0​) rounds of surface-code syndrome extraction. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of 10−310^{-3}10−3, a hierarchical logical processor can achieve 3-4 times higher qubit efficiency than the rotated surface code and 20-30 times shorter logical error-correction cycle times than the yoked surface code.