Error-Detectable Bosonic Entangling Gates with a Noisy Ancilla
Takahiro Tsunoda, James D. Teoh, William D. Kalfus, Stijn J. de Graaf, Benjamin J. Chapman, Jacob C. Curtis, Neel Thakur, S. M. Girvin, Robert J. Schoelkopf
Bosonic quantum error correction has proven to be a successful approach for extending the coherence of quantum memories, but to execute deep quantum circuits, high-fidelity gates between encoded qubits are needed.To that end, we present a family of error-detectable two-qubit gates for a variety of bosonic encodings.From a new geometric framework based on a "Bloch sphere" of bosonic operators, we construct ZZ L (θ) and exponential-SWAP(θ) gates for the binomial, four-legged cat, dual-rail, and several other bosonic codes.The gate Hamiltonian is simple to engineer, requiring only a programmable beam splitter between two bosonic qubits and an ancilla dispersively coupled to one qubit.This Hamiltonian can be realized in circuit QED hardware with ancilla transmons and microwave cavities.The proposed theoretical framework was developed for circuit QED but is generalizable to any platform that can effectively generate this Hamiltonian.Crucially, one can also detect first-order errors in the ancilla and the bosonic qubits during the gates.We show that this allows one to reach error-detected gate fidelities at the 0.01% level with today's hardware, limited only by second-order hardware errors.
Bosonic quantum error correction has proven to be a successful approach for extending the coherence of quantum memories, but to execute deep quantum circuits, high-fidelity gates between encoded qubits are needed.To that end, we present a family of error-detectable two-qubit gates for a variety of bosonic encodings.From a new geometric framework based on a "Bloch sphere" of bosonic operators, we construct ZZ L (θ) and exponential-SWAP(θ) gates for the binomial, four-legged cat, dual-rail, and several other bosonic codes.The gate Hamiltonian is simple to engineer, requiring only a programmable beam splitter between two bosonic qubits and an ancilla dispersively coupled to one qubit.This Hamiltonian can be realized in circuit QED hardware with ancilla transmons and microwave cavities.The proposed theoretical framework was developed for circuit QED but is generalizable to any platform that can effectively generate this Hamiltonian.Crucially, one can also detect first-order errors in the ancilla and the bosonic qubits during the gates.We show that this allows one to reach error-detected gate fidelities at the 0.01% level with today's hardware, limited only by second-order hardware errors.
Fault-tolerant quantum computation with bosonic qubits often necessitates the use of noisy discrete-variable ancillae. In this work, we establish a comprehensive and practical fault-tolerance framework for such a hybrid system and synthesize it with fault-tolerant protocols by combining bosonic quantum error correction (QEC) and advanced quantum control techniques. We introduce essential building blocks of error-corrected gadgets by leveraging ancilla-assisted bosonic operations using a generalized variant of path-independent quantum control. Using these building blocks, we construct a universal set of error-corrected gadgets that tolerate a single-photon loss and an arbitrary ancilla fault for four-legged cat qubits. Notably, our construction requires only dispersive coupling between bosonic modes and ancillae, as well as beam-splitter coupling between bosonic modes, both of which have been experimentally demonstrated with strong strengths and high accuracy. Moreover, each error-corrected bosonic qubit is comprised of only a single bosonic mode and a three-level ancilla, featuring the hardware efficiency of bosonic QEC in the full fault-tolerant setting. We numerically demonstrate the feasibility of our schemes using current experimental parameters in the circuit-QED platform. Finally, we present a hardware-efficient architecture for fault-tolerant quantum computing by concatenating the four-legged cat qubits with an outer qubit code utilizing only beam-splitter couplings. Our estimates suggest that the overall noise threshold can be reached using existing hardware. These developed fault-tolerant schemes extend beyond their applicability to four-legged cat qubits and can be adapted for other rotation-symmetrical codes, offering a promising avenue toward scalable and robust quantum computation with bosonic qubits.
Bosonic quantum error correction represents a route towards significant hardware overhead reduction for fault-tolerant quantum computation. However, controlling quantum harmonic oscillators that encode the quantum information comes with its own challenges. In many platforms such as superconducting circuits and trapped ions, the bosonic degree of freedom is controlled by an ancillary qubit whose decay during a qubit-oscillator gate propagates to the oscillator as a continuous error. Such errors generally lie beyond the scope of errors that the bosonic code is capable of correcting. We introduce the continuous-variable flag: an auxiliary oscillator coupled to the ancilla whose phase-space position encodes the continuous error corrupting the storage mode. After the gate, a heterodyne measurement of the flag estimates this continuous-variable error and a subsequent feedback control undoes it up to a bosonic code stabilizer. The scheme requires no new ingredients, as the flag is driven by the same dispersive coupling, displacements and rotations that implement the gates it is supposed to protect. We construct sequences protecting conditional rotations to all orders in ancilla decay with one flag, and conditional displacements to first order with one flag and to all orders with two. Simulations with realistic circuit-QED parameters predict more than three orders of magnitude fewer logical errors for the parity measurement of a four-component cat code, and a finite-energy GKP logical lifetime near its noiseless-ancilla bound. By discretizing continuous-variable errors, the flags introduced in this work are a useful tool for any hybrid oscillator-qubit processor, and open the route towards fault-tolerant simulation and computation with bosonic modes.
Fault-tolerant quantum computation with bosonic qubits often necessitates the use of noisy discrete-variable ancillae. In this work, we establish a comprehensive and practical fault-tolerance framework for such a hybrid system and synthesize it with fault-tolerant protocols by combining bosonic quantum error correction (QEC) and advanced quantum control techniques. We introduce essential building blocks of error-corrected gadgets by leveraging ancilla-assisted bosonic operations using a generalized variant of path-independent quantum control. Using these building blocks, we construct a universal set of error-corrected gadgets that tolerate a single-photon loss and an arbitrary ancilla fault for four-legged cat qubits. Notably, our construction requires only dispersive coupling between bosonic modes and ancillae, as well as beam-splitter coupling between bosonic modes, both of which have been experimentally demonstrated with strong strengths and high accuracy. Moreover, each error-corrected bosonic qubit is comprised of only a single bosonic mode and a three-level ancilla, featuring the hardware efficiency of bosonic QEC in the full fault-tolerant setting. We numerically demonstrate the feasibility of our schemes using current experimental parameters in the circuit-QED platform. Finally, we present a hardware-efficient architecture for fault-tolerant quantum computing by concatenating the four-legged cat qubits with an outer qubit code utilizing only beam-splitter couplings. Our estimates suggest that the overall noise threshold can be reached using existing hardware. These developed fault-tolerant schemes extend beyond their applicability to four-legged cat qubits and can be adapted for other rotation-symmetrical codes, offering a promising avenue toward scalable and robust quantum computation with bosonic qubits. Published by the American Physical Society 2024
To solve problems of practical importance1,2, quantum computers probably need to incorporate quantum error correction, in which a logical qubit is redundantly encoded in many noisy physical qubits3–5. The large physical-qubit overhead associated with error correction motivates the search for more hardware-efficient approaches6–18. Here, using a superconducting quantum circuit19, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance d = 5 (ref. 10). A stabilizing circuit passively protects cat qubits against bit flips20–24. The repetition code, using ancilla transmons for syndrome measurement, corrects cat qubit phase flips. We study the performance and scaling of the logical qubit memory, finding that the phase-flip correcting repetition code operates below the threshold. The logical bit-flip error is suppressed with increasing cat qubit mean photon number, enabled by our realization of a cat-transmon noise-biased CX gate. The minimum measured logical error per cycle is on average 1.75(2)% for the distance-3 code sections, and 1.65(3)% for the distance-5 code. Despite the increased number of fault locations of the distance-5 code, the high degree of noise bias preserved during error correction enables comparable performance. These results, where the intrinsic error suppression of the bosonic encodings enables us to use a hardware-efficient outer error-correcting code, indicate that concatenated bosonic codes can be a compelling model for reaching fault-tolerant quantum computation. Bosonic qubits can be engineered to feature intrinsic protection against certain kinds of errors, which makes quantum error correction across many bosonic qubits possible with less overhead.
Bosonic codes offer hardware-efficient approaches to logical qubit construction and hosted the first demonstration of beyond-break even logical quantum memory. However, such accomplishments were done for idling information, and realization of fault-tolerant logical operations remains a critical bottleneck for universal quantum computation in scaled systems. Error-transparent (ET) gates offer an avenue to resolve this issue, but experimental demonstrations have been limited to phase gates. Here, we introduce a framework based on dynamic encoding subspaces that enables simple linear drives to accomplish universal gates that are error semi-transparent (EsT) to oscillator photon loss. With an EsT logical gate set of {X, H, T}, we observe a five-fold reduction in infidelity conditioned on photon loss, demonstrate extended active-manipulation lifetimes with quantum error correction, and construct a composite EsT non-Clifford operation using a sequence of eight gates from the set. Our approach is compatible with methods for detectable ancilla errors, offering an approach to error-mitigated universal control of bosonic logical qubits with the standard quantum control toolkit.
Erasure qubits are beneficial for quantum error correction due to their relaxed threshold requirements. While dual-rail erasure qubits have been demonstrated with a strong error hierarchy in circuit quantum electrodynamics, biased-erasure qubits -- where erasures originate predominantly from one logical basis state -- offer further advantages. Here, we realize a hardware-efficient biased-erasure qubit encoded in the vacuum and two-photon Fock states of a single microwave cavity. The qubit exhibits an erasure bias ratio of over 265. By using a transmon ancilla for logical measurements and mid-circuit erasure detections, we achieve logical state assignment errors below 1% and convert over 99.3% leakage errors into detected erasures. After postselection against erasures, we achieve effective logical relaxation and dephasing rates of (6.2ms)−1 and (3.1ms)−1, respectively, which exceed the erasure error rate by factors of 31 and 15, establishing a strong error hierarchy within the logical subspace. These postselected error rates indicate a coherence gain of about 6.0 beyond the break-even point set by the best physical qubit encoded in the two lowest Fock states in the cavity. Moreover, randomized benchmarking with interleaved erasure detections reveals a residual logical gate error of 0.29%. This work establishes a compact and hardware-efficient platform for biased-erasure qubits, promising concatenations into outer-level stabilizer codes toward fault-tolerant quantum computation.