We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped constraints in QAOA when using the parity mapping. The circuits can be implemented on any quantum device with nearest-neighbor connectivity on a square-lattice, using only one gate type and one orientation of two-qubit gates at a time. We find an upper bound for the circuit depth which is independent of the system size. The procedure is readily adjustable to hardware-specific restrictions, such as a minimum required spatial distance between simultaneously executed gates, or gates only being simultaneously executable within a subset of all the qubits, for example a single line.
We present a protocol to encode and decode arbitrary quantum states in the parity architecture with constant circuit depth using measurements, local nearest-neighbor and single-qubit operations only. While this procedure typically requires a quadratic overhead of simultaneous qubit measurements, it allows for a simple and low-depth implementation of logical multi-qubit gates in the parity encoding via code deformation. We discuss how such encoding and decoding schemes can be used to flexibly change the size and shape of the underlying code to enable a more efficient implementation of quantum gates or algorithms. We apply the new findings to the QAOA which leads to a constant depth implementation using local gates at the same optimization performance as the standard, potentially non-local, QAOA approach without the parity encoding. Furthermore, we show that our method can reduce the depth of implementing the quantum Fourier transform by a factor of two when allowing measurements.
Understanding the dynamics of interacting quantum systems is a central goal of quantum simulation. For geometrically local Hamiltonians, locality suggests that digital simulation should retain much of the parallelism of the underlying dynamics. For a target accuracy
ε, we construct a nearest-neighbor quantum circuit that simulates the dynamics of an
n-qubit, time-independent, finite-range Hamiltonian with normalized local interaction strength on a fixed-dimensional lattice for time
T≥1, with circuit depth
O(Tlog(nT/ε)) and gate count
O(nTlog(nT/ε)). This reduces the polylogarithmic overhead of Haah, Hastings, Kothari, and Low to a single logarithm. On logarithmic-scale blocks from the Lieb--Robinson decomposition, a shallow but highly accurate implementation is essential for reducing the circuit depth. Our key observation is that spatial localization also controls the cost of high precision. In each block, the error of a constant-order product formula is compensated for by a correction, yielding exponential accuracy. The correction can be implemented with depth proportional to the block diameter, introducing no additional asymptotic depth scale beyond that required by spatial localization.
Furthermore, we prove an unconditional circuit-depth lower bound for uniform XXZ Hamiltonians: at fixed evolution time
T in the stated regime and sufficiently small fixed error
ε, any nearest-neighbor quantum circuit simulating these dynamics requires depth
Ω(logn/loglogn). This matches our
O(logn) upper bound up to a doubly logarithmic factor, establishing near-optimal circuit depth for lattice Hamiltonian simulation in this regime. Together, these results clarify the role of locality and precision in determining the circuit complexity of quantum dynamics and suggest broader principles for spatially constrained quantum computation.
We present a general strategy for mapping fermionic systems to quantum hardware with square qubit connectivity which yields low-depth quantum circuits, counted in the number of native two-qubit fSIM gates. We achieve this by leveraging novel operator decomposition and circuit compression techniques paired with specifically chosen low-depth fermion-to-qubit mappings and allow for a high degree of gate cancellations and parallelism. Our mappings retain the flexibility to simultaneously optimize for qubit counts or qubit operator weights and can be used to investigate arbitrary fermionic lattice geometries. We showcase our approach by investigating the tight-binding model, the Fermi-Hubbard model as well as the multi-orbital Hubbard-Kanamori model. We report unprecedentedly low circuit depths per single Trotter layer with up to a 70% improvement upon previous state-of-the-art. Our compression technique also results in significant reduction of two-qubit gates. We find the lowest gate-counts when applying the XYZ-formalism to the DK mapping. Additionally, we show that our decomposition and compression formalism produces favourable circuits even when no native parameterized two-qubit gates are available.
We present tools and methods to generalize parity compilation to digital quantum computing devices with arbitrary connectivity graphs and construct circuit implementations for the constraint Hamiltonian of higher-order constrained binary optimization problems. In particular, we show how even nonlocal constraints can be efficiently implemented without expensive SWAP gates. We show how the presented tools can be used to optimize the total circuit depth and CNOT count of the quantum approximate optimization algorithm in the parity architecture and highlight the advantages of the flexible compilation using various examples. We derive the relation between the developed gate sequences and the traditional approach that uses SWAP gates. The result can be applied to improve the implementation of many other nonlocal operators.
We present a formalism based on tracking the flow of parity quantum information to implement algorithms on devices with limited connectivity without qubit overhead, SWAP operations, or shuttling. Instead, we leverage the fact that entangling gates not only manipulate quantum states but can also be exploited to transport quantum information. We demonstrate the effectiveness of this method by applying it to the quantum Fourier transform (QFT) and the quantum approximate optimization algorithm (QAOA) with n qubits. This improves upon all state-of-the-art implementations of the QFT on a linear nearest-neighbor architecture, resulting in a total circuit depth of 5 n − 3 and requiring n 2 − 1 gates. For the QAOA, our method outperforms SWAP networks, which are currently the most efficient implementation of the QAOA on a linear architecture. We further demonstrate the potential to balance qubit count against circuit depth by implementing the QAOA on twice the number of qubits using bilinear connectivity, which approximately halves the circuit depth.
The Quantum Approximate Optimization Algorithm (QAOA) is one of the most promising candidates for achieving quantum advantage over classical computers. However, existing compilers lack specialized methods for optimizing QAOA circuits. There are circuit patterns inside the QAOA circuits, and current quantum hardware has specific qubit connectivity topologies. Therefore, we propose Coqa to optimize QAOA circuit compilation tailored to different types of quantum hardware. Our method integrates a linear nearest-neighbor (LNN) topology and efficiently map the patterns of QAOA circuits to the LNN topology by heuristically checking the interaction based on the weight of problem Hamiltonian. This approach allows us to reduce the number of SWAP gates during compilation, which directly impacts the circuit depth and overall fidelity of the quantum computation. By leveraging the inherent patterns in QAOA circuits, our approach achieves more efficient compilation compared to general-purpose compilers. With our proposed method, we are able to achieve an average of 30% reduction in gate count and a 39x acceleration in compilation time across our benchmarks.