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arXiv:2211.06973

A Variable Node Design with Check Node Aware Quantization Leveraging 2-Bit LDPC Decoding

Philipp H. Mohr, Gerhard Bauch

Published Nov 13, 2022• 0 citations
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Abstract

For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved in the check-to-variable instead of the variable-to-check node messages. The extended optimization leads to a significantly different solution for the compression operation at the variable node. Simulation results for regular LDPC codes confirm that the check node aware design, especially for very coarse quantization with 2- or 3-bit messages, achieves performance gains of up to 0.2 dB - without additional hardware costs. We also show that the 2-bit message resolution enables a very efficient implementation of the check node update, which requires only 2/9 of the 3-bit check node's transistor count and reduces the signal propagation delay by a factor of 4.

DOI
10.48550/arxiv.2211.06973

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For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved in the check-to-variable instead of the variable-to-check node messages. The extended optimization leads to a significantly different solution for the compression operation at the variable node. Simulation results for regular LDPC codes confirm that the check node aware design, especially for very coarse quantization with 2- or 3-bit messages, achieves performance gains of up to 0.2 dB - without additional hardware costs. We also show that the 2-bit message resolution enables a very efficient implementation of the check node update, which requires only 2/9 of the 3-bit check node's transistor count and reduces the signal propagation delay by a factor of 4.
For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved in the check-to-variable instead of the variable-to-check node messages. The extended optimization leads to a significantly different solution for the compression operation at the variable node. Simulation results for regular LDPC codes confirm that the check node aware design, especially for very coarse quantization with 2- or 3-bit messages, achieves performance gains of up to 0.2 dB - without additional hardware costs. We also show that the 2-bit message resolution enables a very efficient implementation of the check node update, which requires only 2/9 of the 3-bit check node's transistor count and reduces the signal propagation delay by a factor of 4.
This paper presents novel techniques for improving the error correction performance and reducing the complexity of coarsely quantized 5G LDPC decoders. The proposed decoder design supports arbitrary message-passing schedules on a base-matrix level by modeling exchanged messages with entry-specific discrete random variables. Variable nodes (VNs) and check nodes (CNs) involve compression operations designed using the information bottleneck method to maximize preserved mutual information between code bits and quantized messages. We introduce alignment regions that assign the messages to groups with aligned reliability levels to decrease the number of individual design parameters. Group compositions with degree-specific separation of messages improve performance by up to 0.4 dB. Further, we generalize our recently proposed CN-aware quantizer design to irregular LDPC codes and layered schedules. The method optimizes the VN quantizer to maximize preserved mutual information at the output of the subsequent CN update, enhancing performance by up to 0.2 dB. A schedule optimization modifies the order of layer updates, reducing the average iteration count by up to 35 %. We integrate all new techniques in a rate-compatible decoder design by extending the alignment regions along a rate-dimension. Our complexity analysis shows that 2-bit decoding can double the area efficiency over 4-bit decoding at comparable performance.
We enhance coarsely quantized LDPC decoding by reusing computed check node messages from previous iterations. Typically, variable and check nodes update and replace old messages every iteration. We show that, under coarse quantization, discarding old messages entails a significant loss of mutual information. The loss is avoided with additional memory, improving performance by up to 0.23 dB. We optimize quantization with a modified information bottleneck algorithm that considers the statistics of old messages. A simple merge operation reduces memory requirements. Depending on channel conditions and code rate, memory assistance enables up to 32% better area efficiency for 2-bit decoding.
We enhance coarsely quantized LDPC decoding by reusing computed check node messages from previous iterations. Typically, variable and check nodes update and replace old messages every iteration. We show that, under coarse quantization, discarding old messages entails a significant loss of mutual information. The loss is avoided with additional memory, improving performance by up to 0.23 dB. We optimize quantization with a modified information bottleneck algorithm that considers the statistics of old messages. A simple merge operation reduces memory requirements. Depending on channel conditions and code rate, memory assistance enables up to 32 % better area efficiency for 2-bit decoding.
Recently, low-resolution LDPC decoders have been introduced that perform mutual information maximizing signal processing. However, the optimal quantization in variable and check nodes requires expensive non-uniform operations. Instead, we propose to use uniform quantization with a simple hardware structure, which reduces the complexity of individual node operations approximately by half and shortens the decoding delay significantly. Our analysis shows that the loss of preserved mutual information resulting from restriction to uniform quantization is very small. Furthermore, the error rate simulations with regular LDPC codes confirm that the uniform quantization causes only minor performance degradation within 0.01 dB compared to the non-uniform alternative. Due to the complexity reduction, especially the proposed 3-bit decoder is a promising candidate to replace 4-bit conventional decoders.
One of the most important units of Low-Density Parity-Check (LDPC) decoders is the Check-Node Unit.Its main task is to find the first two minimum values among incoming variable-to-check messages and return check-tovariable messages.This block significantly affects the decoding performance, as well as the hardware implementation complexity.In this paper, we first propose a modification to the check-node update rule by introducing two optimal offset factors applied to the check-to-variable messages.Then, we present the Check-Node Unit hardware architecture which performs the proposed algorithm.The main objective of this work aims to improve further the decoding performance for 5 th Generation (5G) LDPC codes.The simulation results show that the proposed algorithm achieves essential improvements in terms of error correction performance.More precisely, the error-floor does not appear within Bit-Error-Rate (BER) of 10 -8 , while the decoding gain increases up to 0.21 dB compared to the baseline Normalized Min-Sum, as well as several state-ofthe-art LDPC-based Min-Sum decoders.