As larger, higher-quality quantum devices are built and demonstrated in quantum information applications, such as quantum computation and quantum communication, the need for high-quality quantum memories to store quantum states becomes ever more pressing. Future quantum devices likely will use a variety of physical hardware, some being used primarily for processing of quantum information and others for storage. Here we study the correlation of the structure of quantum information with physical noise models of various possible quantum memory implementations. Through numerical simulation of different noise models and approximate analytical formulas applied to a variety of interesting quantum states, we provide comparisons between quantum hardware with different structure, including both qubit- and qudit-based quantum memories. Our findings point to simple, experimentally relevant formulas for the relative lifetimes of quantum information in different quantum memories and have relevance to the design of hybrid quantum devices.
As larger, higher-quality quantum devices are built and demonstrated in quantum information applications, such as quantum computation and quantum communication, the need for high-quality quantum memories to store quantum states becomes ever more pressing. Future quantum devices likely will use a variety of physical hardware, some being used primarily for processing of quantum information and others for storage. Here we study the correlation of the structure of quantum information with physical noise models of various possible quantum memory implementations. Through numerical simulation of different noise models and approximate analytical formulas applied to a variety of interesting quantum states, we provide comparisons between quantum hardware with different structure, including both qubit- and qudit-based quantum memories. Our findings point to simple, experimentally relevant formulas for the relative lifetimes of quantum information in different quantum memories and have relevance to the design of hybrid quantum devices.
Distributed quantum applications impose requirements on the quality of the quantum states that they consume. When analyzing architecture implementations of quantum hardware, characterizing this quality forms an important factor in understanding their performance. Fundamental characteristics of quantum hardware lead to inherent tradeoffs between the quality of states and traditional performance metrics such as throughput. Furthermore, any real-world implementation of quantum hardware exhibits time-dependent noise that degrades the quality of quantum states over time. Here, we study the performance of two possible architectures for interfacing a quantum processor with a quantum network. The first corresponds to the current experimental state of the art in which the same device functions both as a processor and a network device. The second corresponds to a future architecture that separates these two functions over two distinct devices. We model these architectures as continuous-time Markov chains and compare their quality of executing quantum operations and producing entangled quantum states as functions of their memory lifetimes, as well as the time that it takes to perform various operations within each architecture. As an illustrative example, we apply our analysis to architectures based on Nitrogen- Vacancy centers in diamond, where we find that for presentday device parameters one architecture is more suited to computation-heavy applications, and the other for networkheavy ones. We validate our analysis with the quantum network simulator NetSquid. Besides the detailed study of these architectures, a novel contribution of our work are several formulas that connect an understanding of waiting time distributions to the decay of quantum quality over time for the most common noise models employed in quantum technologies. This provides a valuable new tool for performance evaluation experts, and its applications extend beyond the two architectures studied in this work.
Distributed quantum applications impose requirements on the quality of the quantum states that they consume. When analyzing architecture implementations of quantum hardware, characterizing this quality forms an important factor in understanding their performance. Fundamental characteristics of quantum hardware lead to inherent tradeoffs between the quality of states and traditional performance metrics such as throughput. Furthermore, any real-world implementation of quantum hardware exhibits time-dependent noise that degrades the quality of quantum states over time. Here, we study the performance of two possible architectures for interfacing a quantum processor with a quantum network. The first corresponds to the current experimental state of the art in which the same device functions both as a processor and a network device. The second corresponds to a future architecture that separates these two functions over two distinct devices. We model these architectures as continuous-time Markov chains and compare their quality of executing quantum operations and producing entangled quantum states as functions of their memory lifetimes, as well as the time that it takes to perform various operations within each architecture. As an illustrative example, we apply our analysis to architectures based on Nitrogen-Vacancy centers in diamond, where we find that for present-day device parameters one architecture is more suited to computation-heavy applications, and the other for network-heavy ones. We validate our analysis with the quantum network simulator NetSquid. Besides the detailed study of these architectures, a novel contribution of our work are several formulas that connect an understanding of waiting time distributions to the decay of quantum quality over time for the most common noise models employed in quantum technologies. This provides a valuable new tool for performance evaluation experts, and its applications extend beyond the two architectures studied in this work.
The new quantum era is expected to have an unprecedented social impact, enabling the research of tomorrow in several pivotal fields. These perspectives require a physical system able to encode, process and store for a sufficiently long amount of time the quantum information. However, the optimal engineering of currently available quantum computers, which are small and flawed by several non-ideal phenomena, requires an efficacious methodology for exploring the design space. Hence, there is an unmet need for the development of reliable hardware-aware simulation infrastructures able to efficiently emulate the behaviour of quantum hardware that commits to looking for innovative systematic ways, with a bottom-up approach starting from the physical level, moving to the device level and up to the system level. This article discusses the development of a classical simulation infrastructure for semiconductor quantum-dot quantum computation based on compact models, where each device is described in terms of the main physical parameters affecting its performance in a sufficiently easy way from a computational point of view for providing accurate results without involving sophisticated physical simulators, thus reducing the requirements on CPU and memory. The effectiveness of the involved approximations is tested on a benchmark of quantum circuits — in the expected operating ranges of quantum hardware — by comparing the corresponding outcomes with those obtained via numeric integration of the Schrödinger equation. The achieved results give evidence that this work is a step forward towards the definition of a classical simulator of quantum computers.
An extensively pursued current direction of research in physics aims at the development of practical technologies that exploit the effects of quantum mechanics. As part of this ongoing effort, devices for quantum information processing, secure communication, and high-precision sensing are being implemented with diverse systems, ranging from photons, atoms, and spins to mesoscopic superconducting and nanomechanical structures. Their physical properties make some of these systems better suited than others for specific tasks; thus, photons are well suited for transmitting quantum information, weakly interacting spins can serve as long-lived quantum memories, and superconducting elements can rapidly process information encoded in their quantum states. A central goal of the envisaged quantum technologies is to develop devices that can simultaneously perform several of these tasks, namely, reliably store, process, and transmit quantum information. Hybrid quantum systems composed of different physical components with complementary functionalities may provide precisely such multitasking capabilities. This article reviews some of the driving theoretical ideas and first experimental realizations of hybrid quantum systems and the opportunities and challenges they present and offers a glance at the near- and long-term perspectives of this fascinating and rapidly expanding field.
Abstract Quantum memory—the capacity to faithfully preserve quantum coherence and correlations—is essential for quantum-enhanced technology. There is thus a pressing need for operationally meaningful means to benchmark candidate memories across diverse physical platforms. Here we introduce a universal benchmark distinguished by its relevance across multiple key operational settings, exactly quantifying (1) the memory’s robustness to noise, (2) the number of noiseless qubits needed for its synthesis, (3) its potential to speed up statistical sampling tasks, and (4) performance advantage in non-local games beyond classical limits. The measure is analytically computable for low-dimensional systems and can be efficiently bounded in the experiment without tomography. We thus illustrate quantum memory as a meaningful resource, with our benchmark reflecting both its cost of creation and what it can accomplish. We demonstrate the benchmark on the five-qubit IBM Q hardware, and apply it to witness the efficacy of error-suppression techniques and quantify non-Markovian noise. We thus present an experimentally accessible, practically meaningful, and universally relevant quantifier of a memory’s capability to preserve quantum advantage.
Context: The main obstacle of quantum computing on its way to scalability is the noisy nature of current hardware. Various types of errors lead to incorrect computational results,and measures such as quantum error mitigation are needed to counteract these errors. Many error mitigation techniques require a thorough understanding of the noise and its impact on computations. Therefore, accurate noise models are indispensable to facilitate meaningful quantum computing in the near future. They also enable realistic simulations of quantum devices. Since these devices are currently limited and quantum computing is expensive, researchers typically rely on simulations for testing their algorithms.Objective: In this thesis, we aim to construct a realistic noise model for quantum computing and optimise its model parameters. The model construction should build on the underlying physical processes, and the number of parameters should scale well with the system size. We also address the evaluation and comparison of different noise models by benchmarks using quantum circuits specific to real-world applications. Finally, we aim to develop useful graphical representations of noise models based on the existing quantum circuit model.Method: We present a benchmarking framework for quantum computing noise models and evaluate it based on benchmarking quality attributes from the literature. Moreover, we construct a quantum computing noise model and develop a training procedure for its parameters. We analyse the parameters of the trained noise model and the impact ofdifferent types of errors on computations. We benchmark the noise model with the above approach and compare it to a noise model provided by IBM’s software development kit Qiskit. Finally, we develop an extension of the quantum circuit model to represent noise channels.Result: The benchmarks performed in this thesis show that our noise model predicts noisy hardware behaviour of IBM’s ibmq_manila quantum device equally well as the Qiskit model, if not better, based on quantum circuits commonly used for variational quantum algorithms. Within the trained noise model, readout error has the most detrimental impact on computations. Our benchmarking approach satisfies relevant quality criteria by choosing suitable quantum circuits and objective functions to compare model predictionsto hardware data. Moreover, the quantum circuit model can be extended meaningfully by noise channels.Conclusion: Our benchmarking approach is suitable for evaluating and comparing quantum computing noise models. In future work, volumetric benchmarks should be performed for various noise models and application contexts. The parameter optimisation based on learning with training circuits yields accurate noise models and shows the importance of mitigating measurement error. Different optimisation algorithms and quantum circuits should be explored, and more types of noise should be incorporated into the noise model.