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arXiv:2009.13247

Quantum circuits of CNOT gates

Marc Bataille

Published Sep 24, 2020• 10 citations
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Abstract

We study in detail the algebraic structures underlying quantum circuits generated by CNOT gates. Our results allow us to propose polynomial-time heuristics to reduce the number of gates used in a given CNOT circuit and we also give algorithms to optimize this type of circuits in some particular cases. Finally we show how to create some usefull entangled states when a CNOT circuit acts on a fully factorized state.

DOI
10.48550/arxiv.2009.13247

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We study in detail the algebraic structures underlying quantum circuits generated by CNOT gates. Our results allow us to propose polynomial-time heuristics to reduce the number of gates used in a given CNOT circuit and we also give algorithms to optimize this type of circuits in some particular cases. Finally we show how to create some usefull entangled states when a CNOT circuit acts on a fully factorized state.
CNOT gates are fundamental to quantum computing, as they facilitate entanglement, a crucial resource for quantum algorithms. Certain classes of quantum circuits are constructed exclusively from CNOT gates. Given their widespread use, it is imperative to minimise the number of CNOT gates employed. This problem, known as CNOT minimization, remains an open challenge, with its computational complexity yet to be fully characterized. In this work, we introduce a novel reinforcement learning approach to address this task. Instead of training multiple reinforcement learning agents for different circuit sizes, we use a single agent up to a fixed sizemmm. Matrices of sizes different frommmmare preprocessed using either embedding or Gaussian striping. To assess the efficacy of our approach we trained an agent withm=8m=8m=8, and evaluated it on matrices of sizennnthat ranges from 3 to 15. The results we obtained show that our method overperforms the state of the art algorithm as the value ofnnnincreases.
The design and compilation of correct, efficient quantum circuits is integral to the future operation of quantum computers. This thesis makes contributions to the problems of optimizing and verifying quantum circuits, with an emphasis on the development of formal models for such purposes. We also present software implementations of these methods, which together form a full stack of tools for the design of optimized, formally verified quantum oracles. \n \nOn the optimization side, we study methods for the optimization of Rz and CNOT gates in Clifford+Rz circuits. We develop a general, efficient optimization algorithm called phase folding, which reduces the number of Rz gates without increasing any metrics by computing its phase polynomial. This algorithm can further be combined with synthesis techniques for CNOT-dihedral operators to optimize circuits with respect to particular costs. We then study the optimal synthesis problem for CNOT-dihedral operators from the perspectives of Rz and CNOT gate optimization. In the case of Rz gate optimization, we show that the optimal synthesis problem is polynomial-time equivalent to minimum-distance decoding in certain Reed-Muller codes. For the CNOT optimization problem, we show that the optimal synthesis problem is at least as hard as a combinatorial problem related to Gray codes. In both cases, we develop heuristics for the optimal synthesis problem, which together with phase folding reduces T counts by 42% and CNOT counts by 22% across a suite of real-world benchmarks. \n \nFrom the perspective of formal verification, we make two contributions. The first is the development of a formal model of quantum circuits with ancillary bits based on the Feynman path integral, along with a concrete verification algorithm. The path integral model, with some syntactic sugar, further doubles as a natural specification language for quantum computations. Our experiments show some practical circuits with up to hundreds of qubits can be efficiently verified. Our second contribution is a formally verified, optimizing compiler for reversible circuits. The compiler compiles a classical, irreversible language to reversible circuits, with a formal, machine-checked proof of correctness written in the proof assistant F*. The compiler is structured as a partial evaluator, allowing verification to be carried out significantly faster than previous results.