As we enter the era of useful quantum computers we need to better understand the limitations of classical support hardware, and develop mitigation techniques to ensure effective qubit utilisation. In this paper we discuss three key bottlenecks in near-term quantum computers: bandwidth restrictions arising from data transfer between central processing units (CPUs) and quantum processing units (QPUs), latency delays in the hardware for round-trip communication, and timing restrictions driven by high error rates. In each case we consider a near-term quantum algorithm to highlight the bottleneck: randomised benchmarking to showcase bandwidth limitations, adaptive noisy, intermediate scale quantum (NISQ)-era algorithms for the latency bottleneck and quantum error correction techniques to highlight the restrictions imposed by qubit error rates. In all three cases we discuss how these bottlenecks arise in the current paradigm of executing all the classical computation on the CPU, and how these can be mitigated by providing access to local classical computational resources in the QPU.
As we enter the era of useful quantum computers we need to better understand the limitations of classical support hardware, and develop mitigation techniques to ensure effective qubit utilisation. In this paper we discuss three key bottlenecks in near-term quantum computers: bandwidth restrictions arising from data transfer between central processing units (CPUs) and quantum processing units (QPUs), latency delays in the hardware for round-trip communication, and timing restrictions driven by high error rates. In each case we consider a near-term quantum algorithm to highlight the bottleneck: randomised benchmarking to showcase bandwidth limitations, adaptive noisy, intermediate scale quantum (NISQ)-era algorithms for the latency bottleneck and quantum error correction techniques to highlight the restrictions imposed by qubit error rates. In all three cases we discuss how these bottlenecks arise in the current paradigm of executing all the classical computation on the CPU, and how these can be mitigated by providing access to local classical computational resources in the QPU.
The current stage of quantum computing development is defined by Noisy Intermediate-Scale Quantum (NISQ) devices, which operate with a moderate number of qubits that are inherently susceptible to noise and decoherence. Despite the absence of full error correction, NISQ systems have demonstrated the ability to perform computational tasks that challenge classical simulation under certain conditions. This paper explores the concept of quantum advantage in the NISQ era by analysing prominent algorithmic approaches, benchmarking methodologies, and the practical constraints imposed by contemporary hardware. Hybrid quantum–classical algorithms, sampling-based experiments, and performance metrics are examined to assess the extent to which near-term quantum devices can outperform classical systems. The study finds that while progress toward quantum advantage is evident, significant technical and algorithmic limitations prevent its widespread realization. The paper concludes by identifying key research directions required to bridge the gap between experimental demonstrations and practical quantum computing applications.
Quantum computing may solve selected classes of problems more efficiently than classical computers, with applications in areas such as cryptography, chemistry, and optimization. However, current quantum systems remain limited in scale and reliability and depend on substantial classical-computing support. This thesis investigates this challenge in two complementary contexts: classical simulation, where efficient computation enables the exploration of larger quantum systems; and quantum error correction, where efficient real-time decoding enables more reliable quantum operation.The first part examines the classical simulation of quantum computers, focusing on the computational and memory challenges that limit its scalability. It organizes the field across device, gate, and algorithmic levels, with particular attention to state-vector, path-based, hybrid, and tensor-based methods. The survey relates their computation, memory, data-movement, and communication bottlenecks to acceleration approaches for CPUs, GPUs, FPGAs, and distributed systems. It further highlights recurring optimization strategies, including reduced precision, data compression, parallel execution, improved memory locality, specialized matrix units, and reconfigurable hardware, providing a common framework for current techniques and future acceleration opportunities.The second part addresses the real-time classical processing required for quantum error correction. Starting from a high-accuracy Graph Neural Network surface-code decoder, it applies algorithm-hardware co-design through hardware-guided pruning and retraining, input-graph filtering, quantization, and a custom FPGA architecture. For code distances up to d=7, the resulting designs satisfy both max-latency and average-latency decoding requirements while reducing the logical error rate by 13% and 40%, respectively, compared with the evaluated Minimum Weight Perfect Matching baseline.Together, these works show how classical computer-architecture techniques can support quantum computing from scalable exploration through simulation to reliable operation through real-time error correction.
The Noisy Intermediate-Scale Quantum (NISQ) era, defined by qubit counts in the hundreds and gate error rates that preclude long coherence times, imposes severe constraints on purely quantum computation. The central problem is that achieving practical quantum advantage for real-world tasks must overcome these hardware limitations, yet fault-tolerant quantum computers with full error correction remain years away. To address this, we present a systematic survey of hybrid classical-quantum computing models, in which classical high-performance resources orchestrate the workflow, perform iterative optimization, and apply error mitigation to noisy quantum processing units. Our review encompasses variational quantum algorithms, such as the variational quantum eigensolver and quantum approximate optimization algorithm; classical optimizers tailored for noisy quantum landscapes; error mitigation techniques including zero-noise extrapolation and probabilistic error cancellation; and circuit knitting that partitions large circuits across small QPUs. We find that these hybrid architectures have already demonstrated domain-specific utility in quantum chemistry for molecular ground-state estimation, in logistics and finance for combinatorial optimization, and in machine learning for generative and recommendation models. Notably, they often surpass purely classical or purely quantum approaches on carefully chosen benchmarks. The evidence indicates that hybrid classical-quantum systems are not a temporary stopgap but a durable paradigm. Their role will persist into the early fault-tolerant era, where small, logical qubits will similarly require classical coordination. Consequently, the field urgently demands the establishment of standardized hybrid performance benchmarks, the maturation of robust quantum-classical middleware capable of efficient transpiration and execution management, and holistic co-design frameworks that seamlessly integrate hardware constraints, software stack layers, and application-specific requirements from the outset.
Quantum computing has the potential to solve complex problems that are outside the scope of classical systems, making it a standard shifter. Current devices, which are considered as Noisy Intermediate-Scale Quantum (NISQ) systems, are insufficient in their practical utility due to hardware limitations, error rates, and qubit counts. The dynamic growths wanted to exceed the NISQ era and grow scalable quantum algorithms and architectures that can achieve useful quantum benefit in real-world applications are reviewed in this research. This research gives a comprehensive examination of the complications in scaling quantum systems, adjacent resource efficacy, qubit connectivity, and error correction. In addition to connecting architectural innovations like modular quantum computing, error-resilient circuit design, and distributed quantum systems, the paper provides new hybrid quantum-classical algorithms planned to exploit performance in noisy environments. Results from benchmarking in arenas like machine learning, optimization, and quantum chemistry show how these methods can provide short-term quantum benefit. Lastly, this paper proposes a research roadmap for quantum computing that highlights the requirement of co-designing algorithms, software, and hardware. The goal of this effort is to straighten the progress of quantum systems that can resolve problems in the real world at scale by addressing the inadequacies of NISQ devices and emphasizing scalable solutions.
The maturation of quantum computing from theoretical physics to engineering reality presents a complex landscape for stakeholders navigating the transition from Noisy Intermediate-Scale Quantum (NISQ) devices toward Fault-Tolerant Quantum Computation (FTQC). This report provides a comprehensive, technically rigorous analysis of the current quantum ecosystem, examining the hardware mosaic of leading qubit modalities—superconducting circuits, trapped ions, neutral atoms, and silicon spin qubits—and evaluating them against operational metrics, including coherence times, gate fidelities, and cryogenic infrastructure requirements. We dissect the full software stack, differentiating the near-term utility of error mitigation techniques such as Zero-Noise Extrapolation (ZNE) from the long-term necessity of Quantum Error Correction (QEC) and the milestone of logical qubit break-even. The analysis benchmarks hybrid algorithms (VQE, QAOA) and circuit knitting strategies against current cloud-accessible hardware performance, while also addressing the imminent non-computational impact of PostQuantum Cryptography (PQC) migration. Experimental data synthesised from leading vendor roadmaps and pre-print literature indicate that superconducting platforms currently lead in gate speed (nanosecond regime) but face crosstalk scaling challenges beyond 1,000 qubits. In contrast, trapped-ion and neutral-atom architectures demonstrate superior connectivity and coherence. The report concludes with a grounded, evidence-based five-year projection, identifying high-value vertical use cases in pharmaceuticals and finance, and providing a strategic framework for enterprises to separate quantum hype from tangible commercial opportunity. Future research directions include the realisation of low-overhead Quantum LDPC codes and the development of modular photonic interconnects to scale beyond single-chip architectures.
As current Noisy Intermediate Scale Quantum (NISQ) devices suffer from decoherence errors, any delay in the instruction execution of quantum control microarchitecture can lead to the loss of quantum information and incorrect computation results. Hence, it is crucial for the control microarchitecture to issue quantum operations to the Quantum Processing Unit (QPU) in time. As in classical microarchitecture, parallelism in quantum programs needs to be exploited for speedup. However, three challenges emerge in the quantum scenario: 1) the quantum feedback control can introduce significant pipeline stall latency; 2) timing control is required for all quantum operations; 3) QPU requires a deterministic operation supply to prevent the accumulation of quantum errors.