Recent demonstrations of superconducting quantum computers by Google and IBM and trapped-ion computers from IonQ fueled new research in quantum algorithms, compilation into quantum circuits, and empirical algorithmics. While online access to quantum hardware remains too limited to meet the demand, simulating quantum circuits on conventional computers satisfies many needs. We advance Schrödinger-style simulation of quantum circuits that is useful standalone and as a building block in layered simulation algorithms, both cases are illustrated in our results. Our algorithmic contributions show how to simulate multiple quantum gates at once, how to avoid floating-point multiplies, how to best use data-level and thread-level parallelism as well as CPU cache, and how to leverage these optimizations by reordering circuit gates. While not described previously, these techniques implemented by us supported published high-performance distributed simulations up to 64 qubits. To show additional impact, we benchmark our simulator against Microsoft, IBM and Google simulators on hard circuits from Google.
Recent demonstrations of superconducting quantum computers by Google and IBM and trapped-ion computers from IonQ fueled new research in quantum algorithms, compilation into quantum circuits, and empirical algorithmics. While online access to quantum hardware remains too limited to meet the demand, simulating quantum circuits on conventional computers satisfies many needs. We advance Schrödinger-style simulation of quantum circuits that is useful standalone and as a building block in layered simulation algorithms, both cases are illustrated in our results. Our algorithmic contributions show how to simulate multiple quantum gates at once, how to avoid floating-point multiplies, how to best use data-level and thread-level parallelism as well as CPU cache, and how to leverage these optimizations by reordering circuit gates. While not described previously, these techniques implemented by us supported published high-performance distributed simulations up to 64 qubits. To show additional impact, we benchmark our simulator against Microsoft, IBM and Google simulators on hard circuits from Google.
Developing state-of-the-art classical simulators of quantum circuits is of utmost importance to test and evaluate early quantum technology and understand the true potential of full-blown error-corrected quantum computers. In the past few years, multiple theoretical and numerical advances have continuously pushed the boundary of what is classically simulable, hence the development of a plethora of tools which are often limited to a specific purpose or designed for a particular hardware (e.g. CPUs vs. GPUs). Moreover, such tools are typically developed using tailored languages and syntax, which makes it hard to compare results from, and create hybrid approaches using, different simulation techniques. To support unified and optimized use of these techniques across platforms, we developed HybridQ , a highly extensible platform designed to provide a common framework to integrate multiple state-of-the-art techniques to run on a variety of hardware. The philosophy behind its development has been driven by three main pillars: Easy to Use, Easy to Extend, and Use the Best Available Technology. The powerful tools of HybridQ allow users to manipulate, develop, and extend noiseless and noisy circuits for different hardware architectures. HybridQ supports large-scale high-performance computing (HPC) simulations, automatically balancing workload among different processor nodes and enabling the use of multiple backends to maximize parallel efficiency. Everything is then glued together by a simple and expressive language that allows seamless switching from one technique to another as well as from one hardware to the next, without the need to write lengthy translations, thus greatly simplifying the development of new hybrid algorithms and techniques.
Recent developments in quantum hardware, including the scaling of physical qubits and advanced quantum error correction techniques, have increased the number of reliable logical qubits. However, this progress has introduced new challenges for quantum algorithm developers. Limited access to physical quantum machines and the insufficient performance of classical quantum simulators for near-term scales (∼30 logical qubits) hinder the simulation and validation of quantum algorithms. To address this urgent need for improving simulation performance, we propose a novel end-to-end full-stack solution for Schr¨odinger-style simulation that jointly explores algorithm, software, and hardware optimizations. At the algorithmic level, by identifying the inefficiency in executing complex signed permutations and complex unitary permutation gates, we introduce index redirection and pre-compute merging that significantly reduce data movement and computational complexity. At the hardware level, we propose a reconfigurable dataflow architecture with adaptive memory scheduling and swapping optimizations. At the software level, an end-to-end toolchain is introduced to jointly explore both algorithmic and hardware optimizations. A comprehensive evaluation across a large suite of quantum circuits demonstrates that our work achieves a maximum speedup exceeding 50× over the GPU-based Qiskit baseline.
Summary form only given. Last year saw the first quantum computers realized that can be programmed from a high level user interface to run arbitrary quantum algorithms [1, 2]. While these devices are still small in scale, only comprising a handful of qubits each, they nevertheless allow the implementation of quantum circuits in a way that is basically blind to the underlying hardware itself. This constitutes a new level of development in quantum computer technology for the two leading approaches, trapped atomic ions [1] and superconducting circuits [3]. It also gives us the opportunity to test quantum computers irrespective of their particular physical implementation for the first time. With multiple companies (IBM, Google, Microsoft, as well as several start-ups) aiming for a larger scale device of commercial viability in the near future, benchmarking quantum computers becomes a crucial pursuit and this work is a step in that direction. Our device consists of five171Yb+atomic ions trapped in a Paul trap [1]. Each provides a pristine “atomic clock” qubit in its atomic structure that can be manipulated with laser light and read out via state-dependent fluorescence. Two-qubit gates between any pair are implemented via laser-mediated interaction of qubits through the normal modes of motion in the trap [4] making it a fully connected system.
Quantum computing is a revolutionary approach to computation that leverages the principles of quantum mechanics, enabling computers to process information in fundamentally different ways than classical computers. Unlike traditional bits, which represent data as either 0s or 1s, quantum bits, or qubits, can exist in multiple states simultaneously due to superposition. Additionally, qubits can be entangled, allowing them to be interconnected in ways that enhance computational power and efficiency. This unique behavior has the potential to run certain types of computation tasks much faster than classical computers can, marking a significant leap forward in technology. When building actual quantum computers to run practical quantum algorithms, one needs efficient ways to map the algorithms to the hardware components, similar to compiling classical algorithms onto CPU/GPU hardware. This thesis aims to tackle some of the important problems in the mapping process. First, can we address hardware errors and algorithm errors at the same time? Second, can we build a better circuit complexity metric to inspire better quantum architecture design, and can we design better quantum algorithms and compilation techniques using this improved metric? Lastly, can we use physics-level simulation results to inspire better circuit-level optimization techniques? We hope to provide positive answers to all three questions above through three separate architectural innovations.
We present a comprehensive study of quantum simulation methods and quantum simulators for classical computers. We first study an exhaustive set of 150+ simulators and quantum libraries. Then, we short-list the simulators that are actively maintained and enable simulation of quantum algorithms for more than 10 qubits. As a result, we realize that most efficient and actively maintained simulators have been developed after 2010. We also provide a taxonomy of the most important simulation methods, namely Schrodinger-based, Feynman path integrals, Heisenberg-based, and hybrid methods. We observe that most simulators fall in the category of Schrodinger-based approaches. However, there are a few efficient simulators belonging to other categories. We also make note that quantum frameworks form their own class of software tools that provide more flexibility for algorithm designers with a choice of simulators/simulation method. Another contribution of this study includes the use and classification of optimization methods used in a variety of simulators. We observe that some state-of-the-art simulators utilize a combination of software and hardware optimization techniques to scale up the simulation of quantum circuits. We summarize this study by providing a roadmap for future research that can further enhance the use of quantum simulators in education and research.
While existing quantum hardware resources have limited availability and reliability, there is a growing demand for exploring and verifying quantum algorithms. Efficient classical simulators for high-performance quantum simulation are critical to meeting this demand. However, due to the vastly varied characteristics of classical hardware, implementing hardware-specific optimizations for different hardware platforms is challenging. To address such needs, we propose CAST (Cross-platform Adaptive Schrödinger-style Simulation Toolchain), a novel compilation toolchain with cross-platform (CPU and Nvidia GPU) optimization and high-performance backend supports. CAST exploits a novel sparsity-aware gate fusion algorithm that automatically selects the best fusion strategy and backend configuration for targeted hardware platforms. CAST also aims to offer versatile and high-performance backend for different hardware platforms. To this end, CAST provides an LLVM IR-based vectorization optimization for various CPU architectures and instruction sets, and a PTX-based code generator for Nvidia GPU support. We benchmark CAST against IBM Qiskit, Google QSimCirq, Nvidia cuQuantum backend, and other high-performance simulators. On various 32-qubit CPU-based benchmarks, CAST achieves up to 8.03x speedup than Qiskit. On various 30-qubit GPU-based benchmarks, CAST achieves up to 39.3x speedup than Nvidia cuQuantum backend.