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arXiv:2006.09712 · IEEE Transactions on Quantum Engineering

One-Dimensional Lazy Quantum Walk in Ternary System

Amit Saha, Sudhindu Bikash Mandal, Debasri Saha, Amlan Chakrabarti

Published Jan 1, 2021• 15 citations
arXivHTMLPDF

Abstract

Quantum walks play an important role for developing quantum algorithms and quantum simulations. Here, we introduce a first of its kind one-dimensional lazy quantum walk in the ternary quantum domain and show its equivalence for circuit realization in ternary quantum logic. Using an appropriate logical mapping of the position space on which a walker evolves onto the multiqutrit states, we present efficient quantum circuits for the implementation of lazy quantum walks in one-dimensional position space in ternary quantum system. We also address scalability in terms of$n$-qutrit ternary system with example circuits for a three-qutrit state space.

DOI
10.1109/tqe.2021.3074707

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Quantum walks play an important role for developing quantum algorithms and quantum simulations. Here, we introduce a first of its kind one-dimensional lazy quantum walk in the ternary quantum domain and show its equivalence for circuit realization in ternary quantum logic. Using an appropriate logical mapping of the position space on which a walker evolves onto the multiqutrit states, we present efficient quantum circuits for the implementation of lazy quantum walks in one-dimensional position space in ternary quantum system. We also address scalability in terms ofnnn-qutrit ternary system with example circuits for a three-qutrit state space.
Quantum walks are a promising framework for developing quantum algorithms and quantum simulations. Quantum walks represent an important test case for the application of quantum computers. Here we present different forms of discrete-time quantum walks and show their equivalence for physical realizations. Using an appropriate digital mapping of the position space on which a walker evolves onto the multi-qubit states in a quantum processor, we present different configurations of quantum circuits for the implementation of discrete-time quantum walks in one-dimensional position space. With example circuits for a five qubit machine we address scalability to higher dimensions and larger quantum processors.
Quantum walks are a promising framework for developing quantum algorithms and quantum simulations. They represent an important test case for the application of quantum computers. Here we present different forms of discrete-time quantum walks (DTQWs) and show their equivalence for physical realizations. Using an appropriate digital mapping of the position space on which a walker evolves to the multiqubit states of a quantum processor, we present different configurations of quantum circuits for the implementation of DTQWs in one-dimensional position space. We provide example circuits for a five-qubit processor and address scalability to higher dimensions as well as larger quantum processors.
Synthesis of ternary quantum circuits involves basic ternary gates and logic operations in the ternary quantum domain. Works that define ternary algebra and their applications for ternary quantum logic realization, are very few. In this paper, we express a ternary logic function in terms of projection operations including a new one. We demonstrate how to realize a few new multi-qutrit ternary gates in terms of generalized ternary gates and projection operations. We then employ our synthesis method to design ternary adder circuits which have better cost than that obtained by earlier method.
Basic logic gates and their operations in ternary quantum domain are involved in the synthesis of ternary quantum circuits. Only a few works define ternary algebra for ternary quantum logic realization. In this paper, a ternary logic function is expressed in terms of projection operations including a new one. A method to realize new multi-qutrit ternary gates in terms of generalized ternary gates and projection operations is also presented. We also introduced ten simplification rules for reducing ancilla qutrits and gate levels. Our method yields lower gate cost and fewer gate levels and ancilla qutrits than that obtained by earlier methods for the ternary benchmark circuits. The nnn qutrit ternary sum function is synthesized without any ancilla qutrit by our proposed methodology.
One of the main motivations for using ternary logic systems is the amount of information per circuit line is higher as compared to the corresponding binary logic representation, thereby leading to more compact circuit realizations. This is particularly attractive for quantum computing as qutrits are expensive resources and minimizing their number is one of the main objectives during synthesis. Therefore, ternary reversible logic synthesis has drawn significant attention among researchers. It deals with fundamental unit of information called qutrits that can exist in one of the three states |0>, |1> and |2>. Hence, the aim of this paper is to bridge the knowledge gap for the beginners in this domain than searching the entire space. Therefore, the present work discusses the basic concepts of ternary reversible logic and ternary reversible gates. The detailed discussion of the various ternary reversible logic synthesis will enable the beginners in this domain to understand the ternary reversible logic in a better way.
Abstract In recent years, quantum computing has emerged as a leading approach for accelerating complex computations, leveraging quantum parallelism and entanglement to surpass classical limits. Although numerous quantum circuits based on reversible gates have been proposed, optimizing circuit efficiency remains a critical challenge, particularly in the noisy intermediate-scale quantum era, where error rates and coherence times constrain performance. Ternary quantum computing, which operates on three-level quantum systems (qutrits), offers a promising alternative by reducing circuit complexity and resource overhead. In particular, balanced ternary logic presents advantages over conventional ternary logic by enhancing resource efficiency and potentially mitigating quantum gate error rates. This paper focuses on two key objectives: first, the synthesis of a reversible 1-qutrit comparator circuit using balanced ternary logic, and second, the extension to a generalized n-qutrit comparator. The proposed 1-qutrit comparator achieves notable improvements over existing unbalanced designs, demonstrating a 65% reduction in quantum cost, 50% fewer constant inputs, and a 33% decrease in garbage outputs. These results highlight the potential of balanced ternary logic to enhance the efficiency of quantum circuits, making it a valuable contribution to the development of scalable and error-resilient quantum hardware.