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arXiv:1902.08091 · Leibniz international proceedings in informatics

On the Qubit Routing Problem

Alexander Cowtan, Silas Dilkes, Duncan, Ross, Alexandre Krajenbrink, Will Simmons, Seyon Sivarajah

Published Jan 1, 2019• 132 citations
arXivHTMLPDF

Abstract

We introduce a new architecture-agnostic methodology for mapping abstract quantum circuits to realistic quantum computing devices with restricted qubit connectivity, as implemented by Cambridge Quantum Computing's tket compiler. We present empirical results showing the effectiveness of this method in terms of reducing two-qubit gate depth and two-qubit gate count, compared to other implementations.

DOI
10.4230/lipics.tqc.2019.5

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We introduce a new architecture-agnostic methodology for mapping abstract quantum circuits to realistic quantum computing devices with restricted qubit connectivity, as implemented by Cambridge Quantum Computing's tket compiler. We present empirical results showing the effectiveness of this method in terms of reducing two-qubit gate depth and two-qubit gate count, compared to other implementations.
Quantum circuit compilation is a multi-stage process that translates a high-level quantum circuit representation into a sequence of quantum gates that can be directly executed by a quantum machine. One of the core steps in quantum compilation is mapping, a procedure that transforms a quantum circuit into a semantically equivalent circuit while inserting additional gates to comply with the architectural constraints of the underlying quantum hardware. Current mapping techniques exhibit significant performance degradation—in terms of circuit depth and gate count—when applied to large-scale circuits containing hundreds of thousands of gates or more. In this work, we propose a novel methodology to enhance quantum compiler capabilities by adapting general principles from classical Electronic Design Automation. We model the quantum hardware as being composed of standard cells, onto which portions of the circuit are mapped using a floorplanning-based technique. This contrasts with current state-of-the-art solutions, which perform mapping at the gate level without considering any form of hierarchical abstraction. We use the ChaCha20 stream cipher as a running example to validate and explain our strategy. We evaluate our methodology using two well-known, industrial-grade quantum compilers: IBM Qiskit and Quantinuum TKET. Compared to these compilers, our approach achieves an average circuit depth reduction of 59.78% and 68.85%, respectively, and a gate count reduction of 4.07 % and 6.20 %, respectively. These results are obtained across a large set of randomly generated quantum circuit descriptions in the range of millions of gates, with varying input and output connectivity for each block in the circuit.
One of the key compilation steps in Quantum Computing (QC) is to determine an initial logical to physical mapping of the qubits used in a quantum circuit. The impact of the starting qubit layout can vastly affect later scheduling and placement decisions of QASM operations, yielding higher values on critical performance metrics (gate count and circuit depth) as a result of quantum compilers introducing SWAP operations to meet the underlying physical neighboring and connectivity constraints of the quantum device. In this paper we introduce a novel qubit mapping approach, string-based qubit mapping. The key insight is to prioritize the mapping of logical qubits that appear in longest repeating non-overlapping substrings of qubit pairs accessed. This mapping method is complemented by allocating qubits according to their global frequency usage. We evaluate and compare our new mapping scheme against two quantum compilers (QISKIT and TKET) and two device topologies, the IBM Manhattan (65 qubits) and the IBM Kolkata (27 qubits). Our results demonstrate that combining both mapping mechanisms often achieve better results than either one individually, allowing us to best QISKIT and TKET baselines, yielding between 13% and 17% average improvement in several group sizes, up to 32% circuit depth reduction and 63% gate volume improvement.
‘‘Qubit routing” refers to the task of modifying quantum circuits so that they satisfy the connectivity constraints of a target quantum computer. This involves inserting SWAP gates into the circuit so that the logical gates only ever occur between adjacent physical qubits. The goal is to minimise the circuit depth added by the SWAP gates. In this article, we propose a qubit routing procedure that uses a modified version of the deep Q-learning paradigm. The system is able to outperform the qubit routing procedures from two of the most advanced quantum compilers currently available (Qiskit and t ∣ | ∣ ket ⟩ \rangle ⟩ ), on both random and realistic circuits, across a range of near-term architecture sizes (with up to 50 qubits).
Near-term quantum computers often have connectivity constraints, i.e. restrictions, on which pairs of qubits in the device can interact. Optimally mapping a quantum circuit to a hardware topology under these constraints is a difficult task. While numerous approaches have been proposed to optimize qubit routing, the resulting gate count and depth overheads of the compiled circuits remain high due to the short-range coupling of qubits in many near-term devices. Resource states, such as Bell or Einstein-Podolsky-Rosen (EPR) pairs, can be used to mediate operations that facilitate long-range interactions between qubits. In this work, we studied some of the practical trade-offs involved in using resource states for qubit routing. We developed a method that leverages an existing state-of-the-art compiler to optimize the routing of circuits with both standard gates and EPR mediated remote controlled-NOT gates. This was then used to compile different benchmark circuits for a square grid topology, where a fraction of the qubits are used to store EPR pairs. We demonstrate that EPR-mediated operations can substantially reduce the total number of gates and depths of compiled circuits when used with an appropriate optimizing compiler that accounts for practical overheads. Our results highlight the relevance of developing efficient compilation tools that can integrate EPR-mediated operations.
One of the key compilation steps in Quantum Computing (QC) is to determine an initial logical to physical mapping of the qubits used in a quantum circuit. The impact of the starting qubit layout can vastly affect later scheduling and placement decisions of QASM operations, yielding higher values on critical performance metrics (gate count and circuit depth) as a result of a quantum compilers introducing communication operations to meet the underlying physical neighboring and connectivity constraints of the quantum device.We present our ongoing work on qubit mapping with affine abstractions, which aims to compute effective initial qubit layouts. The key assumption is that the quantum program is represented in an affine representation, a property which permits us to apply aggressive program analyses to determine the potential of sharing qubit accesses among groups of quantum operations prescribed by linear and affine relations. We present preliminary results demonstrating the effectiveness of our novel approach on 69 quantum circuits, while using the QISKIT compiler on IBM Tokyo and Google Sycamore, obtaining between 16% and 21% average improvement on circuit depth and 24%–47% improvement on the number of added gates.
Executing quantum circuits on currently available quantum computers requires compiling them to a representation that conforms to all restrictions imposed by the targeted architecture. Due to the limited connectivity of the devices' physical qubits, an important step in the compilation process is to map the circuit in such a way that all its gates are executable on the hardware. Existing solutions delivering optimal solutions to this task are severely challenged by the exponential complexity of the problem. In this paper, we show that the search space of the mapping problem can be limited drastically while still preserving optimality. The proposed strategies are generic, architecture-independent, and can be adapted to various mapping methodologies. The findings are backed by both, theoretical considerations and experimental evaluations. Results confirm that, by limiting the search space, optimal solutions can be determined for instances that timeouted before or speed-ups of up to three orders of magnitude can be achieved.