Medium-scale quantum devices that integrate about hundreds of physical qubits are likely to be developed in the near future. However, these devices will lack the resources for realizing quantum fault tolerance. Therefore, the main challenge of exploring the advantage of quantum computation is to minimize the impact of device and control imperfections without complete logical encoding. Quantum error mitigation is a solution satisfying the requirement. Here, we demonstrate an error mitigation protocol based on gate set tomography and quasi-probability decomposition. One- and two-qubit circuits are tested on a superconducting device, and computation errors are successfully suppressed. Because this protocol is universal for digital quantum computers and algorithms computing expected values, our results suggest that error mitigation can be an essential component of near-future quantum computation.
Medium-scale quantum devices that integrate about hundreds of physical qubits are likely to be developed in the near future. However, these devices will lack the resources for realizing quantum fault tolerance. Therefore, the main challenge of exploring the advantage of quantum computation is to minimize the impact of device and control imperfections without complete logical encoding. Quantum error mitigation is a solution satisfying the requirement. Here, we demonstrate an error mitigation protocol based on gate set tomography and quasi-probability decomposition. One- and two-qubit circuits are tested on a superconducting device, and computation errors are successfully suppressed. Because this protocol is universal for digital quantum computers and algorithms computing expected values, our results suggest that error mitigation can be an essential component of near-future quantum computation.
Quantum computing holds the promise of solving problems that are intractable for classical computers, with applications ranging from optimization and materials simulation to cryptography. It achieves this by leveraging the exponentially scaling dimensionality of the space encoding quantum information and by executing algorithms on quantum registers in superposition states – a feature often referred to as quantum parallelism. However, while encoding information in computational units capable of exploring a continuous set of quantum states enables exponential scaling of computational power with system size, quantum systems are also more susceptible to errors than their classical counterparts. These errors take the form of both control errors, where miscalibration of the control pulses causes coherent errors on the qubit states, as well as incoherent errors due to energy relaxation and dephasing. Scaling quantum systems to run useful algorithms involving hundreds or thousands of logical qubits will require quantum error correction. In this approach, quantum information is redundantly encoded across an entangled state of many physical qubits. This has enabled experimental demonstrations across various platforms – including ion traps, superconducting circuits, and neutral atoms – showing that encoded quantum states can be preserved beyond the coherence times of the constituting physical qubits. However, quantum state preservation is only one component needed for scalable quantum computing. To execute algorithms, it is also necessary to implement quantum gates on and between encoded qubits, in a way that maintains fault tolerance by preserving the ability to correct errors as they occur during the computation. In the first part of this thesis, we demonstrate the implementation of an error-corrected quantum operation that entangles two logical qubits. This is achieved by performing lattice surgery on a distance-three surface code qubit, resulting in a logical Bell state encoded in distance-three repetition codes, which enable the correction of single bit-flip errors. We further introduce techniques to benchmark and characterize the performance of logical operations, including applying the protocol to arbitrary logical input states and performing logical quantum process tomography. Together, these results constitute one of the first realizations of error-corrected lattice surgery in superconducting circuits. While quantum error correction can correct errors provided they occur with sufficiently low frequency, it may fail when many qubits experience errors simultaneously. In the second part of this thesis, we therefore shift focus to a specific error mechanism known to cause correlated errors in superconducting circuits – quasiparticle-induced decoherence. In this case, various forms of energy deposition on the quantum device can break Cooper pairs into quasiparticles, which may subsequently diffuse to the tunnel junction and interact with the qubit state, thereby causing decoherence. In this thesis, we investigate the impact of quasiparticle tunneling on qubit performance, with a focus on infrared-induced quasiparticles. We compare the sensitivity of niobium-based qubits to those made from tantalum – a material that has gained interest in recent years following demonstrations of qubits with improved coherence times based on this material. Using a thermal radiator source, we show that the performance of tantalum qubits may be limited by infrared-induced quasiparticles in typical superconducting circuit experimental setups. By employing both ambient and in-line infrared filters, we investigate the effectiveness of different filtering strategies and develop best practices for engineering cryogenic environments for superconducting quantum processors. The results presented in this thesis contribute to the advancement of quantum computing based on superconducting circuits by implementing and characterizing quantum error-corrected operations, and by investigating quasiparticles as a source of decoherence, along with strategies to improve infrared filtering and signal conditioning in cryogenic environments for future fault-tolerant quantum computing.
Fault-tolerant quantum computing (FTQC) is a form of universal quantum computing that suppresses physical errors via quantum error correction (QEC). On the other hand, it is expected that the available code distance and the T-gate count will be restricted in the early years of FTQC. Meanwhile, quantum error mitigation (QEM) was recently introduced for suppressing errors in noisy intermediate-scale quantum (NISQ) devices; it improves the computation accuracy of near-term quantum algorithms with its overhead being a greater number of samples. In this work, we integrate QEC and QEM into an efficient FTQC architecture that effectively increases the code distance and T-gate count. Our scheme will dramatically alleviate the required qubit count by tens of percent at the cost of a constant multiplicative sampling overhead within 102 in a wide range of regimes from the post-NISQ era to early FTQC regime, which necessitates the order of from 104 to 1010 logical operations. While it has been widely believed that there do not exist useful applications in post-NISQ regimes due to a chasm between the NISQ and FTQC regimes such as overheads for encoding and T-gate distillations, our scheme can continuously bridge the two distinct regimes.
Quantum computing promises to revolutionize several scientific and technological domains through fundamentally new ways of processing information. Among its most compelling applications is digital quantum simulation, where quantum computers are used to replicate the behavior of other quantum systems. This could enable the study of problems that are otherwise intractable on classical computers, transforming fields such as quantum chemistry, condensed matter physics, and materials science. Despite this potential, realizations of practical quantum advantage for relevant problems are hindered by imperfections of current devices. This also affects quantum hardware based on superconducting circuits which is among the most advanced and scalable platforms. The envisaged long-term solution of fault-tolerant quantum computers that correct their own errors remains out of reach mainly due to the associated qubit number overhead. As a result, the field has developed strategies that combine quantum and classical resources, exploit hardware-native operations, and employ error mitigation techniques to extract meaningful results from noisy data. This doctoral thesis contributes to this broader effort by exploring methods for advancing quantum simulation across the full computational stack, including hardware-level innovations, refined techniques for noise modeling and error mitigation, and algorithmic improvements enabled by efficient measurement processing.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
A long-standing challenge in quantum computing is developing technologies to overcome the inevitable noise in qubits. To enable meaningful applications in the early stages of fault-tolerant quantum computing, devising methods to suppress post-correction logical failures is becoming increasingly crucial. In this work, we propose and experimentally demonstrate the application of zero-noise extrapolation, a practical quantum error mitigation technique, to error correction circuits on superconducting processors. By amplifying the noise on physical qubits, the circuits yield outcomes that exhibit a predictable dependence on noise strength, following a polynomial function determined by the code distance. This property enables the effective application of polynomial extrapolation to mitigate logical errors. Our experiments demonstrate a universal reduction in logical errors across various quantum circuits, including fault-tolerant circuits of repetition and surface codes. We observe a favorable performance in multi-round error correction circuits, indicating that this method remains effective when the circuit depth increases. These results advance the frontier of quantum error suppression technologies, opening a practical way to achieve reliable quantum computing in the early fault-tolerant era. Quantum error mitigation refers to techniques that reduce, rather than correct, errors in quantum computing. Here the authors demonstrate zero-noise extrapolation applied to quantum error correction circuits on superconducting processors, effectively reducing logical errors and advancing early fault-tolerant quantum computing.
In Phys. Rev. A 108, L060402 (2023), we introduced a Bayesian measurement error mitigation algorithm, which leveraged complete information from the readout signal, and validated the protocol on a quantum device with five superconducting qubits. Here, we present an improved algorithm's implementation, tailored for multiqubit experiments on near-term superconducting qubit quantum devices. In particular, we provide a detailed algorithm workflow, from calibrating the detector response functions to the postprocessing of measurement outcomes, offering a computationally efficient solution for the output size typical of current quantum computing devices. We show how the numerical representation of the noise function affects the performance of the error mitigation algorithm and test the convergence criteria. We benchmark our protocol on actual quantum computers with superconducting qubits, where the readout signal encodes the measurement information as unprocessed analog data before qubit state assignment. Finally, we compare the performance of our algorithm against other measurement error mitigation methods, such as iterative Bayesian unfolding and the Mthree method, and show how our method can be integrated on top of other readout error mitigation protocols.