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arXiv:0803.2316

On the CNOT-cost of TOFFOLI gates

Vivek Shende, Igor L. Markov

Published Mar 15, 2008• 7 citations
arXivHTMLPDF

Abstract

The three-input TOFFOLI gate is the workhorse of circuit synthesis for classical logic operations on quantum data, e.g., reversible arithmetic circuits. In physical implementations, however, TOFFOLI gates are decomposed into six CNOT gates and several one-qubit gates. Though this decomposition has been known for at least 10 years, we provide here the first demonstration of its CNOT-optimality. We study three-qubit circuits which contain less than six CNOT gates and implement a block-diagonal operator, then show that they implicitly describe the cosine-sine decomposition of a related operator. Leveraging the canonicity of such decompositions to limit one-qubit gates appearing in respective circuits, we prove that the n-qubit analogue of the TOFFOLI requires at least 2n CNOT gates. Additionally, our results offer a complete classification of three-qubit diagonal operators by their CNOT-cost, which holds even if ancilla qubits are available.

DOI
10.48550/arxiv.0803.2316

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The three-input TOFFOLI gate is the workhorse of circuit synthesis for classical logic operations on quantum data, e.g., reversible arithmetic circuits. In physical implementations, however, TOFFOLI gates are decomposed into six CNOT gates and several one-qubit gates. Though this decomposition has been known for at least 10 years, we provide here the first demonstration of its CNOT-optimality. We study three-qubit circuits which contain less than six CNOT gates and implement a block-diagonal operator, then show that they implicitly describe the cosine-sine decomposition of a related operator. Leveraging the canonicity of such decompositions to limit one-qubit gates appearing in respective circuits, we prove that the n-qubit analogue of the TOFFOLI requires at least 2n CNOT gates. Additionally, our results offer a complete classification of three-qubit diagonal operators by their CNOT-cost, which holds even if ancilla qubits are available.
The three-input \TOFFOLI\ gate is the workhorse of circuit synthesis for classical logic operations on quantum data, e.g., reversible arithmetic circuits. In physical implementations, however, \TOFFOLI\ gates are decomposed into six \CNOT\ gates and several one-qubit gates. Though this decomposition has been known for at least 10 years, we provide here the first demonstration of its \CNOT-optimality. We study three-qubit circuits which contain less than six \CNOT\ gates and implement a block-diagonal operator, then show that they implicitly describe the cosine-sine decomposition of a related operator. Leveraging the canonical nature of such decompositions to limit one-qubit gates appearing in respective circuits, we prove that the nnn-qubit analogue of the \TOFFOLI\ requires at least 2n2n2n \CNOT\ gates. Additionally, our results offer a complete classification of three-qubit diagonal operators by their \CNOT -cost, which holds even if ancilla qubits are available.
The three-input TOFFOLI gate is the workhorse of circuit synthesis for classical logic oper-ations on quantum data, e.g., reversible arithmetic circuits. In physical implementations,however, TOFFOLI gates are decomposed into six CNOT gates and several one-qubit gates.Though this decomposition has been known for at least 10 years, we provide here thefirst demonstration of its CNOT-optimality. We study three-qubit circuits which containless than six CNOT gates and implement a block-diagonal operator, then show that theyimplicitly describe the cosine-sine decomposition of a related operator. Leveraging thecanonical nature of such decompositions to limit one-qubit gates appearing in respectivecircuits, we prove that the n-qubit analogue of the TOFFOLI requires at least 2n CNOTgates. Additionally, our results offer a complete classification of three-qubit diagonaloperators by their CNOT-cost, which holds even if ancilla qubits are available.
State-of-the-art studies on quantum layout synthesis have proposed various approaches based on the assumption that the input circuit is only composed of single-qubit and two-qubit gates. This assumption greatly simplifies the layout synthesis problem, and thus they only require ensuring that all controlled-NOT (CNOT) gates satisfy the hardware constraints imposed by a given coupling graph. However, during the design of quantum circuits, multi-controlled Toffoli (MCT) gates are usually used to better characterize the function of the circuits. Directly decomposing them into single and two-qubit gates with a fixed routine ignores the flexibility and optimization opportunity provided by various decomposition (i.e., logic synthesis) possibilities and thus suffers from sub-optimal results. This article proposes a co-optimization approach for quantum logic and layout synthesis. The MCT gates are first decomposed into Toffoli gates, and an efficient qubit mapping checking process is proposed to optimally solve the SWAP-free layout synthesis problem by automatically determining the decomposition result of each Toffoli gate. If a SWAP-free result cannot be found, the proposed algorithm flow is then used to obtain a solution that minimizes the total cost that simultaneously counts the cost caused by the different decomposition methods for Toffoli gates and the cost induced by SWAP gates. Compared with a state-of-the-art method, the proposed approach reduces the number of additional CNOT gates by 16% with around 25X runtime speedup for the cases with SWAP-free solutions, which cannot be obtained without the co-optimization approach.
The minimization of Quantum Cost (QC), specifically the number of Toffoli gates, is a primary objective in the synthesis of reversible arithmetic circuits. For decades, the Peres Full Adder has been considered the benchmark for minimal realizations, requiring 2 Toffoli gates and a Quantum Cost of 12. In this note, we propose a novel reversible Full Adder circuit that utilizes only one Toffoli gate and four CNOT gates. The proposed design achieves a Quantum Cost of 9, representing a 25% reduction compared to the Peres structure, while maintaining a competitive logical depth of 4. We rigorously verify the logic and demonstrate that the reduction is achieved through the automated synthesis framework recently proposed by the authors.
We study the implementation of quantum channels with quantum computers while minimizing the experimental cost, measured in terms of the number of controlled-not (cnot) gates required (single-qubit gates are free). We consider three different models. In the first, the quantum circuit model (QCM), we consider sequences of single-qubit and cnot gates and allow qubits to be traced out at the end of the gate sequence. In the second (RandomQCM), we also allow external classical randomness. In the third (MeasuredQCM) we also allow measurements followed by operations that are classically controlled on the outcomes. We prove lower bounds on the number of cnot gates required and give near-optimal decompositions in almost all cases. Our main result is a MeasuredQCM circuit for any channel from mmm qubits to nnn qubits that uses at most one ancilla and has a low cnot count. We give explicit examples for small numbers of qubits that provide the lowest known cnot counts.
Quantum circuit synthesis is the procedure of automatically generating quantum circuits to represent specified functions. A common gate in quantum circuits is the reversible Toffoli gate, a type of generalized controlled NOT operation. There are physical barriers to implementing large quantum gates. Large Toffoli gates can be decomposed into equivalent sets of smaller, quantum elementary gates. The cost of a quantum circuit can be measured by counting the number of elementary gates in the circuit after all gates have been decomposed. Traditionally this decomposition is done independently for each gate in the circuit. This thesis identifies pairs of gates that, if decomposed together, result in fewer total elementary gates than they would otherwise. These improvements are incorporated into a simple decomposition algorithm which manipulates the circuit in order to search for such pairs. The decomposition algorithm is compared to a naive implementation, and the resulting gate costs are presented and compared.